AMD Athlon 64 Revisão E trás suporte SSE3

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AMD Athlon 64 Revision E adds SSE3 Support

As we discovered most recently, AMD's 90nm CPUs are of a brand new revision that featured a number of bug fixes and performance improvements. Internally AMD refers to this CPU revision as Revision D. However we noticed something very interesting when looking at the latest AMD roadmaps while in Taiwan: the 90nm chips listed as San Diego and Venice (Athlon 64 FX and Athlon 64 respectively) claimed SSE3 support as a feature, but the current 90nm chips do not have SSE3 support.

We went around to quite a few manufacturers asking what the difference was between the 90nm chips shipping today and the 90nm chips that supposedly feature SSE3 support, and unfortunately we were left with very little information - until we learned to ask for the right thing.

Internally, AMD's San Diego and Venice CPUs are referred to as nothing more than Athlon 64 Revision E chips. Revision E includes even more bug fixes and performance improvements over those we found in Revision D, including support for the 13 new instructions that were added with Prescott, more commonly known as SSE3.

The performance enhancements that go along with Revision E chips include some optimizations to the Athlon 64's memory controller. The more optimized memory controller improves bandwidth efficiency with regards to unified graphics memory accesses; given that the only type of graphics that uses system memory (and thus the on-die memory controller) is integrated graphics, it's safe to say that the Rev E chips will offer better integrated graphics performance.

The first Revision E CPUs will begin shipping in early 2005. AMD also has plans to introduce an Athlon 64 4200+ towards the middle of 2005; they are not listing whether the part will feature a 512KB or 1MB L2 cache, but it will most likely run at 2.6GHz. The Athlon 64 FX-57 is also listed on the roadmap as a 2H-05 part, it's specifications are also unclear but we'd expect it to be a 2.8GHz part with a 1MB L2 cache. Both the Athlon 64 FX-57 and Athlon 64 4200+ appear to be 90nm parts built on the San Diego and Venice cores, respectively.

AMD's 2005 roadmap did not specifically list anything faster than the 4200+, although the classic "> 4200+" was present on the roadmap to indicate potentially faster parts.

On the Intel side of things we heard the name Cedar Mill thrown around a bit more. In the past some have referred to Intel's dual core Pentium 4 as Cedar Mill, but we now know that is Smithfield. This time we heard Cedar Mill referred to as the first 1066MHz FSB Pentium 4s that aren't Extreme Edition chips. Cedar Mill is supposed to be out in the 2nd half of 2005, which supports a claim we made in our recent review of the Pentium 4 3.46EE: "the 3.46EE will be followed up by the 3.73EE as the only two chips to support the faster FSB for almost a year."

So what does having no mainstream 1066MHz FSB chips until the end of next year mean? It means that Intel is holding out for Glenwood and Lakeport and that Sunday's launch of the 1066MHz FSB was merely a gimmick. The 925XE will be buried as the chipset that offered support for two CPUs that no one bought, while Glenwood and Lakeport will be the knights in shining armor that brought 1066MHz FSB support to all.

Intel seems to have learned from their 925X and 915 chipset launches - multiple fundamental technology changes without performance gains don't go over well. Glenwood and Lakeport will be able to support faster DDR2 (DDR2-667), 1066MHz FSB and dual core support upon their release, not to mention that lower latency DDR2 should be available by then (mid next year) and PCI Express graphics should be much more prevalent as well.
Clicar para expandir...

http://www.anandtech.com/printarticle.aspx?i=2264

Já todos devem ter visto este artigo mas será interessante pensar o que valerá em termos de performance a inclusão destas 13 novas instruções.

O OC seguramente que se manterá pelo menos:)
 
Se for como o SS3 dos P4, quase nadinha...

Demora sempre bastante a aparecerem softwares optimizados para essas instruções.
Normalmente os ciclos entre a disponibilidade e as optimizacoes andam nos 18/24 meses... porque nem toda a gente vai a correr reprogramar os seus programas para fazer uso disso. Normalmente quem salta logo no comboio sao os CAD's e afins...

Tambem ao preço que custam... hehehe
 
Eu suponho que esse 4200+ que estará para vir será baseado no fx-55 a 0,09.
Penso que a diferença de perfomance da rev. D para a E será minima, excepto situações de encoding.. não vou esperar por essa revisão para pegar num athlon 64! :)

[]´s
 
Enquanto não houver aplicações que saibam tirar partido, até podem trazer SSE18... :)

Já as SSE2 demoraram algum tempo até se tirar real partido.
 
Raptor disse:
Enquanto não houver aplicações que saibam tirar partido, até podem trazer SSE18... :)
Clicar para expandir...
Vais dizer que não querias SSE18...:D:D:D


Até que é bom saber que vão ter mas só será realmente bom a longo prazo quando for implementado em optimizações no software.
 
Eeerrr... N sabia k tb haviam "bugs" nos processadores... afinal o k é k isso ker dizer? K os anteriores tinham algum problema (n era só no software k havia bugs)?
 
Stormgiant disse:
:lol: :lol: :lol: :lol: :lol:
Clicar para expandir...

Post muito produtivo, sem duvida. Parabens.
A verdade é que tambem não entendo o significado de bugs a nivel de processador, mas mesmo que entendesse, não iria dar uma resposta dessas. Parece que estás a gozar com a falta de conhecimentos dos outros.

Se alguém puder tirar a duvida do SteelBoy (assim como minha) agradeço... ;)
 
Nao se trata de bug, mas sim da implementacao das instrucoes SSE3 numa proxima revisao dos A64, a E.

Os Prescott ja teem esta instrucao e nao se verificou reducao a nivel de oc.
 
pois, acho que não ha bugs em hardware, ker dizer, não é suposto. Se desse alguma bronca simplesmente cortam as implementações do processador e pronto :)

Tou a gostar disto... mais uns meses e tenho um athlon 64 com uma boa mb a chamar por mim :D
 
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