Zarolho
Power Member
L3 cache isn’t coming for no reason
TALKING WITH ENGINEERS can be a refreshing experience, unlike most of the marchitectural mumbo-jumbo I often encounter. One such conversation happened since I proffered the AMD DDR-II 1066 story during SnowBIT in Hangover. The engineer comes from the wonderful world of DRAM development.
Why was DDR-II 667 support scrapped, and why is AMD gearing up towards DDR-II 800 and possibly faster memory clocks? The reason is the latency of DDR-II, which is considered to be catastrophic for companies with direct access to the memory. This wasn’t a problem for only AMD. Remember the products from ATI and Nvidia with DDR-II memory some time ago, most notably the 256MB version of Radeon 9800Pro and the "dustbuster" known as the GeForce FX5800.
The reason why AMD decided to scrap DDR-II 667 was because it had predicted, or perhaps just hoped, that by the time of migration to the new socket, the latencies of DDR-II would fall to the DDR-I level, and the ideal pick would be 2.5 and 3 latencies at the worst. Sadly for AMD, things went in the other direction and the only logical conclusion was to implement support for higher memory speeds. As memory standards develop, there is a possibility that AMD will add support for faster DDR-II memory by just updating the microcode, but things are far more complicated than that.
The answer is simple in theory. Add another level of cache, go for a big one and you’re home free. In fact, by creating a larger L3 cache, AMD will have the opportunity to reduce the size of L2 cache and save die space. 64+64 L1, 512KB or 1MB L2 and 2-4MB of L3 are the first things that comes to mind. The cache would of course, keep all two or four cores happy and keep the data flowing.
Of course, there is also another possibility. A 256-bit memory controller, doubling the bandwidth of current 128-bit and adding complexity to the memory configuration with at least four populated slots. µ
http://www.theinquirer.net/?article=30513
TALKING WITH ENGINEERS can be a refreshing experience, unlike most of the marchitectural mumbo-jumbo I often encounter. One such conversation happened since I proffered the AMD DDR-II 1066 story during SnowBIT in Hangover. The engineer comes from the wonderful world of DRAM development.
Why was DDR-II 667 support scrapped, and why is AMD gearing up towards DDR-II 800 and possibly faster memory clocks? The reason is the latency of DDR-II, which is considered to be catastrophic for companies with direct access to the memory. This wasn’t a problem for only AMD. Remember the products from ATI and Nvidia with DDR-II memory some time ago, most notably the 256MB version of Radeon 9800Pro and the "dustbuster" known as the GeForce FX5800.
The reason why AMD decided to scrap DDR-II 667 was because it had predicted, or perhaps just hoped, that by the time of migration to the new socket, the latencies of DDR-II would fall to the DDR-I level, and the ideal pick would be 2.5 and 3 latencies at the worst. Sadly for AMD, things went in the other direction and the only logical conclusion was to implement support for higher memory speeds. As memory standards develop, there is a possibility that AMD will add support for faster DDR-II memory by just updating the microcode, but things are far more complicated than that.
The answer is simple in theory. Add another level of cache, go for a big one and you’re home free. In fact, by creating a larger L3 cache, AMD will have the opportunity to reduce the size of L2 cache and save die space. 64+64 L1, 512KB or 1MB L2 and 2-4MB of L3 are the first things that comes to mind. The cache would of course, keep all two or four cores happy and keep the data flowing.
Of course, there is also another possibility. A 256-bit memory controller, doubling the bandwidth of current 128-bit and adding complexity to the memory configuration with at least four populated slots. µ
http://www.theinquirer.net/?article=30513
Por acaso nunca me tinha lembrado do 5 ser dos ns... Então venham lá as BH-2 k eu n me importo nada...