Processador AMD Demos 6 and 12 core Opteron- Istanbul, Magny-Cour (pag2)

Vai sair várias boards EATX (12"x13" (305x330mm)) que muitas caixas para desktop suportam.
Para um PC normal, para jogos pouco ganham com boards para servidores/workstations...
 
anjo2 disse:
Vai sair várias boards EATX (12"x13" (305x330mm)) que muitas caixas para desktop suportam.
Para um PC normal, para jogos pouco ganham com boards para servidores/workstations...
Clicar para expandir...

Sim, mas onde queria chegar é que aquela board, sendo dual socket para os novos Xeons, "só" está a custar 260$, o que comparando com muitas boards x58 e não tendo nada de errado a nível de features, é um óptimo preço.
Claro que depois o preço dos processadores e da memória já não é tão amigável.
 
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Enter Interlagos and Valencia; AMD's first processors based on the revolutionary [for AMD, of course] CPU architecture. According to released information, a 170% increase in number of cores [from 6 to 16] should result in 400% performance increase in Floating-Point calculations on a clock-per-clock basis. Add variant clocks to that and we have a receipt for a hard battle in server/workstation segment. Valencia's theoretical numbers should show similar jumps, but overall performance will differ due to difference in memory controller: Valencia comes with a dual-channel, 144-bit memory controller while Interlagos features a quad-channel, 288-bit memory controller.

According to the call, it can be expected that Bulldozer will be a seriously big deal for the CPU space. While Bobcat targets the low-end and wants to go after spreading ARM and its Cortex series, Bulldozer is the first new CPU architecture for AMD since Hammer series in 2003. While Patla wasn't willing to disclose interesting architectural details that would explain the impressive jump in projected performance for the Bulldozer-based Interlagos processor.
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http://www.brightsideofnews.com/new...re-interlagos-is-based-on-bulldozer-core.aspx
 
Será desta que a AMD vai competir com a Intel em clock per clock?

Só que em 2011 o Interlagos vai apanhar o sandy-bridge
 
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Mais detalhes do Hexa-core da Amd em sistemas 2 e 4 sockets.

Magny-Cours MCM and links

Here is where the fun begins, with the MCM itself. The red links are memory channels, two per die, four per socket. Green, blue and grey are all HT, with wide lines representing 16-bit links, narrow ones are 8-bit. It doesn't take much to realize that things are complex here.

The wide green link off the bottom is is the external I/O, basically the connection to the chipset, one per socket. Actually, since you can "ungang" the 16-bit HT link into two 8-bit HT links, you could theoretically put two chipsets off of one socket. That said, this is very unlikely to happen, it is much easier to add one off each socket.

This link is non-coherent HT (ncHT), meaning that it can't be used for CPU to CPU interconnects. All of the other links, blue and grey are cache-coherent HT (ccHT). If you are sharp eyed, you will notice that the blue ccHT links between the dies on package are different widths.

The 'extra' link is extra for a good reason, but more on this later. AMD added it to the mix because it could, more or less for free. It increased the bandwidth between the cores by 50%, but real world performance does not go up by much because the cores are rarely bandwidth bound.

Of more interest is that, because these dies are soldered to the package, not run through a socket, they are of a set length and made of known materials. AMD took some liberties here, basically because it can keep tolerances much tigher; it upped the bandwidth on these links a lot. Unfortunately, AMD did not say how much. The links are ccHT like all the other, just notably faster and likely lower latency as well.

In a four socket system using the 'old way' AMD did things, that is, a square, two of these three links were used to connect the chips to the two neighbors. A chip in the top left would be connected to the one on the right, and the one below, but not the socket diagonally across. The third was not used.

Diagonal connections could be done, but rarely if ever actually were done. The third ccHT connection was used to connect two 4-way squares to make an 8-way system. While this was a good thing for packing more CPUs into a box, it was hobbled by the latency caused by multiple hops across HT links. CPU 0 loading from CPU 7's memory might need four hops to get to the data and four hops to get back. Add in cache coherency, and you had those hops taking the whole system to its knees.

The way around this is to directly connect each socket to every other one in the system. On a two socket box, that is easy, you just connect point A to point B. On a four socket, you make a square with an X in the middle, exactly what AMD traded off to allow for eight sockets on socket F and before.

With the new socket G34, AMD did just that. The grey 8-bit ccHT link is basically a diagonal link, the X in the square. If there was only one die in each socket, that would work wonderfully, problem solved! Unfortunately, G34 has two dies per socket, and they are connected to the two dies in the other socket using one of those 8-bit links per die.

On a two socket system, the links directly between the dies are 16-bit and the ones going diagonally are 8-bit. Since there are two full ccHT links per die, there are four per socket to connect everything on a four socket system. To connect between sockets, you don't need the full bandwidth that a 16-bit HT links brings.

In the end, each socket is connected to every other socket directly, but every die is only connected to every other die on a two socket system. The worst case in G34 is to have any die two hops away from any other die. It all looks like this.
Clicar para expandir...

http://www.semiaccurate.com./2009/08/24/amd-outs-socket-g34/
 
AMD Demos 48-core ''Magny-Cours'' System, Details Architecture

AMD Demos 48-core ''Magny-Cours'' System, Details Architecture
Earlier slated coarsely for 2010, AMD fine-tuned the expected release time-frame of its 12-core "Magny-Cours" Opteron processors to be within Q1 2010. The company seems to be ready with the processors, and has demonstrated a 4 socket, 48 core machine based on these processors. Magny Cours holds symbolism in being one of the last processor designs by AMD before it moves over to "Bulldozer", the next processor design by AMD built from ground-up. Its release will provide competition to Intel's multi-core processors available at that point.

AMD's Pat Conway at the IEEE Hot Chips 21 conference presented the Magny-Cours design that include several key design changes that boost parallelism and efficiency in a high-density computing environment. Key features include: Move to socket G34 (from socket-F), 12-cores, use of a multi-chip module (MCM) package to house two 6-core dies (nodes), quad-channel DDR3 memory interface, and HyperTransport 3 6.4 GT/s with redesigned multi-node topologies. Let's put some of these under the watch-glass.

​


Socket and Package
Loading 12 cores onto a single package and maintaining sufficient system and memory bandwidth would have been a challenge. With the Istanbul six-core monolothic die already measuring 346 mm² with a transistor-load of 904 million, making something monolithic twice the size is inconceivable, at least on the existing 45 nm SOI process. The company finally broke its contemptuous stance on multi-chip modules which it ridiculed back in the days of the Pentium D, and designed one of its own. Since each die is a little more than a CPU (in having a dual-channel memory controller, AMD chooses to call it a "node", a cluster of six processing cores that connects to its neighbour on the same package using one of its four 16-bit HyperTransport links. The rest are available to connect to neighbouring sockets and the system in 2P and 4P multi-socket topologies.

The socket itself gets a revamp from the existing 1,207-pin Socket-F, to the 1,974-pin Socket G34. The high pin-count ensures connections to HyperTransport links, four DDR3 memory connections, and other low-level IO.


​

Multi-Socket Topologies
A Magny-Cours Opteron processor can work in 2P and 4P systems for up to 48 physical processing cores. The multi-socket technologies AMD devised ensures high inter-core and inter-node bandwidth without depending on the system chipset IO for the task. In the 2P topology, one node from each socket uses one of its HyperTransport 16-bit links to connect to the system, the other to the neighbouring node on the package, and the remaining links to connect to the nodes of the neighbouring socket. It is indicated that AMD will make use of 6.4 GT/s links (probably generation 3.1). In 4P systems, it uses 8-bit links instead, to connect to three other sockets, but ensures each node is connected to the other directly, on indirectly over the MCM. With a total of 16 DDR3 DCTs in a 4P system, a staggering 170.4 GB/s of cumulative memory bandwidth is achieved.


​

Finally, AMD projects a up to 100% scaling with Magny-Cours compared to Istanbul. Its "future-silicon" projected for 2011 is projected to almost double that.

 
AMD Magny Cours CPU-Z Validation

AMD Magny Cours CPU-Z Validation
Here's the first CPU-Z validation of AMD's 12-core Magny Cours processor. Whatever details the existing version of CPU-Z does read, perfectly matches the specifications of the processor sketched out so far. Firstly, it's based on AMD's upcoming socket G3 package that marks Opteron's transition to high-level integration within a single package. With 1,974 pins, socket G3 is able to provide as many as six 16-bit HyperTransport 3.1 links, and four DDR3 memory channels. The package is one of AMD's first multi-chip modules, that houses two six-core dies (dubbed "nodes"), onto one package, and connects the two using a HyperTransport link.

Each node has 6 x 512 KB of L2 cache and 6 MB L3 cache shared between the six cores. Out of 6 MB, 1 MB of the cache is reserved for low-level system operations, namely the HT Assist (probe filter) that aims to lower memory subsystem latencies, reduces queuing delays due to lower HyperTransport traffic overhead, and minimizes probe traffic to increase system bandwidth. The CPU-Z reading of 10 MB total chip L3 cache is spot-on. Also seen on the validation page are details on the reference motherboard, called "AMD Dinar", that uses SR5690 (same chip as 890FX) + SB750 chipset. The CPU-Z validation can be found here.

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Fonte:http://www.techpowerup.com/103347/AMD_Magny_Cours_CPU-Z_Validation.html
 
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Não sei se repararam, mas naquela plataforma estão dois CPUs com 12 núcleos cada um. Ou seja, 24 núcleos.

É mesmo caso para dizer Holly Shit.
 
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Winjer disse:
Não sei se repararam, mas naquela plataforma estão dois CPUs com 12 núcleos cada um. Ou seja, 32 núcleos.

É mesmo caso para dizer Holly Shit.
Clicar para expandir...


hmmmm acho que são 2 CPUS de 6 cores cada um... ou seja o mesmo que a intel vez para os core 2 que era 2 processadores de um nucleo cada um...

Mas mesmo que seja 2 CPUS de 12 cores cada um:

12
+12
_____
24


ehehehe
 
matavelhos disse:
hmmmm acho que são 2 CPUS de 6 cores cada um... ou seja o mesmo que a intel vez para os core 2 que era 2 processadores de um nucleo cada um...

Mas mesmo que seja 2 CPUS de 12 cores cada um:

12
+12
_____
24


ehehehe
Clicar para expandir...

A intel nos core 2 dual core é um único cpu de dois cores, os core2quad [pelo menos os Q6600/q6700] é que são dois dual-core embolachados, penso eu..

Nos pentium 4 dual é que a intel também utilizou esta técnica..

A AMD nos dual core e quad's é que acho que não tinha ainda feito isto, era tudo um único cpu com vários cores, agora este de 12 cores é que é a junção de 2 cpu's de 6 cores cada..
Isto não é sinónimo de má performance, tudo depende da forma como se interligam os 'dois cpu's'..
 
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