AMD quer comprar a Xilinx por 30 mil milhões

[Dark Kaeser]

AMD-Xilinx and AI Updates at AMD Financial Analyst Day 2022​

e claro o software integrando tudo no ROCm

https://www.servethehome.com/amd-xilinx-ai-updates-at-amd-financial-analyst-day-2022/


por outro lado a convergência dos modelos chiplets, quer da Xilinx quer da AMD, e do "xPU interconnect"

AMD Technology Roadmap from AMD Financial Analyst Day 2022​

https://www.servethehome.com/amd-technology-roadmap-from-amd-financial-analyst-day-2022/

 

[Dark Kaeser]

Now Comes The Hard Part, AMD: Software​

From the moment the first rumors surfaced that AMD was thinking about acquiring FPGA maker Xilinx, we thought this deal was as much about software as it was about hardware.

After the Financial Analyst Day presentations last month, we have been mulling the one by Victor Peng, formerly chief executive officer at Xilinx and now president of the Adaptive and Embedded Computing Group at AMD.

https://www.nextplatform.com/2022/07/08/now-comes-the-hard-part-amd-software/

 

[Dark Kaeser]

AMD 400G Adaptive Exotic SmartNIC Architecture at HC34​

This is the processing subsystem PSX. LPD is the 4-core (Arm R52) Low Power Domain. FPD is the 8 core (Arm A78E) Full Power Domain. There are also some hardware accelerators here for things like TLS.

OVS is a big application for these devices. Most solutions in the space cover this.

VirtIO is really interesting because it allows a cloud (public or on-prem) provider to virtualize resources and present them to tenants/ customers in a standardized way, and then manage infrastructure separately on the back-end.

Here is a very interesting use case where there the NIC is being used for custom flows on the networking side. This is a pretty common use case.

The NIC can virtualize NVMe.

This is the solution that we showed with the Intel IPU solution in the article/ video above.

With the FPGA, this can be a PCIe root, similar to an ASIC DPU. One can then put NVMe off of the device and avoid using a traditional host.

We actually showed this concept with the NVIDIA BlueField-2 DPUs a few months ago in ZFS without a Server Using the NVIDIA BlueField-2 DPU.

Final Words​

It is very confusing to call this a SmartNIC at this point. It is certainly something more capable than most DPUs or at least more flexible. Still, we probably need to re-brand Exotic for folks. AMD needs to address this because it now has Pensando which competes with this solution in some markets.

The card makes a lot of sense for AMD as Xilinx has a business making these types of FPGA NICs. Having a new generation is great. We were told by AMD prior to this announcement that this is not a product announcement, so this is a future product apparently. Hopefully, we get to see one live in the future, especially as AMD goes PCIe Gen5.

https://www.servethehome.com/amd-400g-adaptive-exotic-smartnic-architecture-at-hc34/

 

[Dark Kaeser]

AMD-Xilinx XDMA Driver Being Merged For Linux 6.3​

Adding to all of the other AMD changes coming with Linux 6.3 is now also having the AMD-Xilinx XDMA driver in tow. Getting this XDMA subsystem driver upstreamed is important for unblocking more Xilinx-based feature code to be merged into the Linux kernel.

The AMD-Xilinx XDMA subsystem is used for high performance data transfers between the host memory and the Alveo PCIe card's Direct Memory Access (DMA) subsystem. In addition to being used by the Alveo cards, the Versal ACAP DMA and Bridge subsystems also make use of XDMA.

The XDMA driver was previously maintained by Xilinx out-of-tree so it's nice seeing it all come together finally upstream for Linux 6.3.

https://www.phoronix.com/news/AMD-Xilinx-XDMA-Linux-6.3

Não faltará muito até terem a parte do modelo de programação e SW unificado.

 

[Dark Kaeser]

Isto é que será o tal 1º produto, digo eu.

Entretanto a AMD lá enviou uma imagem da dita demo

AMD Versal 400Gbps In-Line IPSec Demo​

At OFC 2023, AMD showed off the new demo. The importance of in-line IPSec is that it requires some form of acceleration. While in the 1GbE/ 10GbE generation, one could use CPU cores for IPSec, in the 100GbE and over speed range, it is a workload that needs acceleration. AMD for its part is using the Xilinx Versal Premium IP. We covered the AMD Xilinx Versal Premium ACAP previously.

Key aspects of AMD’s 400G IPSec demonstration include:

• 100G-400G scalable DCMAC and HSC hardened blocks.
• 400G Security policies and Security database lookup with AMD’s CAM & STCAM IPs.
• Integration of IPSec control and data plane with up to 32K tunnel setup using industry-standard strongSwan APIs running on the AMD platform using EPYC processors and Versal Premium series devices. (Source: AMD)

AMD has the ability to tie 400G I/O, hardened IP blocks, and the FPGA-based fabric together to build a 400G IPSec in-line accelerator.

https://www.servethehome.com/amd-versal-400gbps-in-line-ipsec-demo/

 

[Dark Kaeser]

AMD Introduces Alveo MA35D Media Accelerator

AMD today announced the AMD Alveo MA35D media accelerator featuring two 5 nm, ASIC-based video processing units (VPUs) supporting the AV1 compression standard and purpose-built to power a new era of live interactive streaming services at scale.

Purpose-Built Video Processing Unit
The Alveo MA35D utilizes a purpose-built VPU to accelerate the entire video pipeline. By performing all video processing functions on the VPU, data movement between the CPU and accelerator is minimized, reducing overall latency and maximizing channel density with up to 32x 1080p60, 8x 4Kp60, or 4x 8Kp30 streams per card. The platform provides ultra-low latency support for the mainstream H.264 and H.265 codecs and features next-generation AV1 transcoder engines delivering up to a 52% reduction in bitrate for bandwidth savings versus a comparable software implementation.

https://www.techpowerup.com/306910/amd-introduces-alveo-ma35d-media-accelerator

https://www.xilinx.com/applications/data-center/video-imaging/alveo-ma35d.html

Edit:

https://twitter.com/i/web/status/1643966446668480512

 

[Nemesis11]

And energy efficiency is the other major gain over the older U30 card – and what AMD considers a significant edge over their competition, as well. The formal TDP of the card is 50 Watts, but in practice AMD is finding that the typical power consumption of the card is closer to about 35 Watts, or a hair over 1W per stream for 1080p60.

All told, AMD is making some fairly aggressive image quality claims with the Alveo MA35D; H.264 and H.265 image quality should be similar to x264 Medium and x265 Medium presets respectively, while the card’s AV1 encoding quality should be comparable to x265 slow. These comparisons are based on VMAF scores, and what settings it takes to achieve similar scores. Or to frame things in a bitrate basis, using AV1 AMD says the MA35D can deliver the same image quality as the Alveo U30 in H.264 mode at 55% of the bitrate (a 1.8x efficiency improvement).

Finally, although secondary to the video encode capabilities of the MA35D, it’s interesting to note that the management processors in the VPU have shifted from Arm to RISC-V. Whereas the U30’s processors used quad core Cortex-A53 cores, the MA35D VPU uses a pair of quad core RISC-V cores – though AMD doesn’t specify whose. The RISC-V architecture has been quietly pushing out Arm for management controllers such as these, and this is another example of that transition in action.

According to AMD, the Alveo is sampling to partners now. The company expects to begin production shipments in the third quarter of the year, with a suggested retail price of $1595.

https://www.anandtech.com/show/1880...accelerator-av1-video-encode-at-1w-per-stream

Pouco mais de 1W por stream 1080p60 parece ser bastante interessante.
Também interessante é termos mais uma empresa que migra os processadores de management de ARM para RISC-V. Como a placa da geração anterior usava 4 Cores ARM A53, não devem ser Cores < 32 bit usados em micro-controladores. EDIT: So agora vi o link do Twitter colocado pelo @Dark Kaeser . 2 Cores RISC-V 64 bit.

 

[Dark Kaeser]

O actual "líder" da AMD Research, funcionário da AMD há 15 anos vai ser substituído nessas funções pelo CTO da XIlinx

Head Of AMD’s Influential Research Group Leaves Amid Other Exec Changes​

The head of AMD’s influential research group is departing the chip designer 15 years after founding the division that has made crucial contributions in areas like AI, high-performance computing and advanced memory.

Alan Lee, the head of AMD Research, announced Friday on LinkedIn that he has decided to “move on” from the Santa Clara, Calif.-based company, where his group “created a large number of new technologies for the good of AMD, the compute ecosystem and humankind.”

An AMD spokesperson told CRN that the AMD Research team will be led by Ivo Bolsens, who is senior vice president and CTO of the company's adaptive, embedded and AI group. Bolsens joined AMD through its $49 billion acquisition of FPGA designer Xilinx last year. At Xilinx, he was responsible for advanced technology development and research laboratories as senior vice president and CTO.

Created as an “entrepreneurial research laboratory,” AMD Research’s mission is to “drive disruptive and revolutionary technology innovation to increase AMD’s growth and profitability,” according to a note from Lee on AMD’s website. To that end, Lee said AMD Research has “been extraordinarily successful.”

“AMD Research helped enable a renaissance at AMD, emphasizing AI and machine learning, high-performance computing, and the efficient use of system resources,” he wrote on AMD’s website

Beyond high-performance computing, AMD Research’s focus areas also include advanced memory, which includes processing-in-memory, 3D stacked memory and intelligent memory systems.

https://www.crn.com/news/components...research-group-leaves-amid-other-exec-changes


Deixando de lado o motivo da saída, não deixa de ser interessante a opção para a substituição dessa divisão vir da Xilinx, que também tinha a sua divisão de I&D nas mesmas áreas.

 

[Dark Kaeser]

https://twitter.com/i/web/status/1648732111182917632

 

[Dark Kaeser]

AMD Acquires Mipsology to Deepen AI Inference Software Capabilities​

I am pleased to share that today we welcome the talented team from Mipsology, a leader in AI software and long-standing AMD partner based in Palaiseau, France, to the AMD family.

Mipsology’s highly skilled software team has proven expertise in delivering AI software and solutions running on top of AMD adaptive computing silicon, and will join the AMD AI Group to help further accelerate our customer engagements and expand our AI software development capabilities. Specifically, the team will help develop our full AI software stack, expanding our open ecosystem of software tools, libraries and models to pave the way for streamlined deployment of AI models running on AMD hardware.

The company’s flagship Zebra AI software supports industry frameworks including TensorFlow, PyTorch, and ONNX Runtime and will help accelerate AMD solutions for AI workloads. The integration also supports the AMD Unified AI (UAI) Software Stack, which delivers a cohesive AI training and inference interface across edge, endpoint and cloud.

https://community.amd.com/t5/corpor...y-to-deepen-ai-inference-software/ba-p/626433

 

[Dark Kaeser]

AMD Versal Premium VP1902 Next-Gen Chiplet FPGA at Hot Chips 2023​

This is an AMD Versal Premium VP1902 adaptive SoC that is designed to be massive in scale.

This is the inter-die connectivity and how the chip is packaged. FPGAs need to not just have chiplet-to-chiplet connectivity, but they often need to support extremely high-speed and dense external I/O.

Here is the chiplet in the previous VU19P.

Now AMD is talking about performance criteria scaling to more devices.

https://www.servethehome.com/amd-versal-premium-vp1902-next-gen-chiplet-fpga-at-hot-chips-2023/

 

[Dark Kaeser]

AMD Automotive

https://www.phoronix.com/news/AMD-Ryzen-Embedded-V2000A

Ryzen V2000 (zen2+Radeon Vega) para infotainment, tudo o resto é Xilinx.

 

[Dark Kaeser]

AMD Embedded Plus Announced​

AMD is now selling its Ryzen Embedded and Versal parts together as part of AMD Embedded+. This is not the single-package solution some have been waiting for. Instead, they are on the same PCB.

One of the big features of the new offering is that it is designed for sensor processing using the x86 and FPGA parts for what they are best at.

Something that may be obvious, looking at the slides above and below, is that these are two packages connected via PCIe.

Further enhancing its capability, the AMD Versal AI Edge adaptive SoCs on the Embedded+ motherboard offer adaptable I/O options for real-time sensor input and industrial networking. This includes interfacing with LiDAR, RADAR, and other delicate and sophisticated sensors necessary for modern embedded systems in the industrial, medical, and automotive sectors. The platform's support for various product-level sensor interfaces, such as GMSL and Ethernet-based vision protocols, means it is designed and ready for integration into complex, sensor-driven systems.

Also announced is a series of expansion boards that significantly broaden support for the Embedded+ architecture. The Octo GMSL Camera I/O board is particularly noteworthy for its ability to interface with multiple cameras simultaneously. It is undoubtedly suitable for high bandwidth vision-based systems, integral to sectors such as advanced driver-assistance systems (ADAS) and automated surveillance systems. These systems often require the integration of numerous image inputs for real-time processing and analysis, and the Octo GMSL board is engineered to meet this demand specifically.

If you want, you can get a Zen+ based AMD Ryzen Embedded R2314 SoC. Typically, embedded products have longer lifecycles. We can see this has ten years of planned availability. The chip itself was launched in 2022, so it is likely around two years into its ten year cycle. At the same time, Zen+ is around six years old already.

Of course, with the Ryzen embedded, we get a GPU with display outputs as well as the encode/ decode functions. We do not get AV1 since this is an older set of encode/ decode IP.

The Versal AI edge architecture has a lot of the I/O, DSP functions, and so forth for the platform.

The bigger aspect is that AMD is going to market with partners today with the new platform. For example, the Sapphire VPR-4616-MB has the AMD Versal AI Edge 2302 along with the AMD Ryzen Embedded R2314. It has functions for a PC, but also has an expansion connector for I/O boards.

That is a big part of the AMD Embedded+ story. The idea is to reduce time to market for folks building solutions by making it easier to pair AMD’s embedded x86 and FPGA portfolios.

The idea with Embedded+ is not just the AMD Ryzen Embedded R2314 and Versal AI Edge 2302. AMD sees this as spanning multiple generations of embedded CPUs and different FPGA variants.

AMD also has Zen 2 and Zen 4 embedded CPUs that it can pair with much larger FPGAs.

AMD plans to offer a pre-built infrastructure version for this solution, but there will also be a fully customizable version.

https://www.servethehome.com/amd-embedded-plus-announced/
https://www.anandtech.com/show/2125...hitecture-ryzen-embedded-with-versal-together