Athlon 64 Revision E adds SSE3 Support
Internally, AMD's San Diego and Venice CPUs are referred to as nothing more than Athlon 64 Revision E chips. Revision E includes even more bug fixes and performance improvements over those we found in Revision D, including support for the 13 new instructions that were added with Prescott, more commonly known as SSE3.
The performance enhancements that go along with Revision E chips include some optimizations to the Athlon 64's memory controller. The more optimized memory controller improves bandwidth efficiency with regards to unified graphics memory accesses; given that the only type of graphics that uses system memory (and thus the on-die memory controller) is integrated graphics, it's safe to say that the Rev E chips will offer better integrated graphics performance.
The first Revision E CPUs will begin shipping in early 2005. AMD also has plans to introduce an Athlon 64 4200+ towards the middle of 2005; they are not listing whether the part will feature a 512KB or 1MB L2 cache, but it will most likely run at 2.6GHz. The Athlon 64 FX-57 is also listed on the roadmap as a 2H-05 part, it's specifications are also unclear but we'd expect it to be a 2.8GHz part with a 1MB L2 cache. Both the Athlon 64 FX-57 and Athlon 64 4200+ appear to be 90nm parts built on the San Diego and Venice cores, respectively.
AMD's 2005 roadmap did not specifically list anything faster than the 4200+, although the classic "> 4200+" was present on the roadmap to indicate potentially faster parts.