Designing for power efficiency
- Better idle detection – get idle components to low power stages fast
- Better activity detection – get idle components back to full performance fast
- Better power state selection – reduce the penalty of power state transition
7nm Vega – making the best graphics engine even better
Reduced engine size for better efficiency and higher performance
- 2x wide Data Fabric interface for power efficient data transfer
- Graphics low power state transition optimization
- 25% higher peak graphics clock
- 77% higher peak memory bandwidth
Delivered Results
- Up to 59% higher Time Spy performance per Compute Unit
- 1.79 TFLOPs (FP32)
Infinity Fabric (Power Optimized for Mobile)
- Up to 75% better power efficiency
7nm technology, dynamic power optimization in the fabric switches, double bus width from graphics to fabric improve pj/bit
- Up to 77% higher memory bandwidth at low power
DDR4-3200 and LPDDR4x-4266
Memory Controller Design
- Two memory controllers
- Each controller can support 1×65 for DDR4 or 2×32 using virtual channels for LPDDR4x
- 4×32 LPDDR4x4266 (68.3 GB/s peak) OR 2×64 (DDR4-4200 (51.2 GB/s)
Enhanced IO Connectivity while maintaining the same package body size as Picasso
- Improved Memory Technology (DDR4 up to 3200, LPDDR4X up to 4266)
- Added 4 PCIe lanes – NVME storage, Wireless Wifi 6, 5G
- Added 2 USB Ports – Support for increasing Number of Devices
Better Mobile Boost with STT V2
- Boost duration can be extended for the user by up to 4X by considering chassis temp
- Surace temp of the notebook can be managed with a closed-loop
- V2 STT simplifies OEM EC designs by pulling chassis thermal calculations into the SoC
- Works alongside AMP STAMP technology
AMD SmartShift
- dGPU and SoC operate as a single virtual domain
- dGPU performance and thermal counters are shared across PCIe
- SoC natively managed dGPU boost like its own iGPU with the Infinity Fabric Contol Units
- Performance governed by platform DPTC settings
Activity Based Clock Controls – power-efficient clock controls
- System management controller observes activity monitors throughout the cores and interconnect
- This activity information is used to adjust clocks up or down, as appropriate for the activity level of each IP block
- Examples; ramp frequency on each core as demand increases or interconnect buses ramp up or down to balance QoS and power
- Threshold levels can also be adjusted by higher-level inputs such as OS settings or user preferences