R520's commercial availability was scheduled for introduction roughly one year after R420, i.e. late spring to summer 2005. Initially R520 was on target for this type of timescale, and just three days after the release of the Radeon X850 series, based on R480, the refresh to R420/R423, ATI received their first packaged R520 chips, ready for the bring-up process. Things appeared to be going as planned, with sightings of the product in operation at E3; however, following on from that nothing appeared, even with NVIDIA's release of their next generation G70 product ATI didn't announce any products. Soon stories of leaking issues appeared and eventually Dave Orton, ATI's CEO, announced that the scheduled release had indeed been pushed back due to "a variety of design issues".
According to public reports ATI noticed that as late as July, issues occurred that prevented the R520 core being clocked close to its target speeds, which is consistent with leakage issues. Curiously, the issue did not occur across all their 90nm products - ATI had already delivered Xenos to Microsoft using the same 90nm process R520 does, and other derivatives of the R520 line suffered the same issue (RV530) but others did not (RV515) - the fact R520 and RV530 share the same memory bus, while RV515 and Xenos have different memory busses is not likely to be coincidental in this case. ATI were open about talking about the issue they faced bringing up R520, sometimes describing the issue in such detail that only Electronic Engineers are likely to understand, however their primary issue when trying to track it down was that it wasn't a consistent failure - it was almost random in its appearance, causing boards to fail in different cases at different times, the only consistent element being that it occurs at high clockspeeds. Although, publicly, ATI representatives wouldn't lay blame on exactly were the issue existed, quietly some will point out that when the issue was eventually traced it had occurred not in any of ATI's logic cells, but instead in a piece of "off-the-shelf" third party IP whose 90nm library was not correct. Once the issue was actually traced, after nearly 6 months of attacking numerous points where they felt the problems could have occurred, it took them less than an hour to resolve in the design, requiring only a contact and metal change, and once back from the fab with the fix in place stable, yield-able clockspeeds jumped in the order of 160MHz.