Nemesis11 disse:Mais on topic:
Como é que ele vai ser barato com um die size de 206mm^2 ?
Aqui dão como 221 mm^2 e 234 milhoes transistores.
The multi-core processor claims supercomputer-like levels of performance with clock speeds in excess of 4GHz.
A first prototype of the device expected to power the Playstation 3 has a 221mm² die, uses 234 million transistors and is made using 90nm process technology.
The version of Cell announced today contains eight 64-bit floating point processors, referred to as synergistic processor elements (SPEs). Along side these is a 64-bit Power processor capable of running two threads.
SPEs take 128-bit operands, split into four 32-bit words. Up to 128 operands can be stored in the register file.
Each 2.5x5.81mm SPE can issue two instructions per cycle to seven execution units using two pipelines. There is no out of order execution.
Connecting up the processing units is the element interconnect bus (EIB), comprising four 128-bit rings and a 64-bit tag running at half the processor clock.
The busses connect to the SPEs through local memory, 256kbyte for each SPE. The developers have tested the memories to 5.4GHz at 1.3V and 52°C.
There are 15 separate power domains on the chip. Ten digital thermometers monitor the chip at various points to alert the system of thermal problems.
The Cell processor uses two technologies from Rambus: a chip-to-chip interconnect, FlexIO, formerly known as "Redwood"; and an eXtended Data RAM (XDR) interface. Sony indicated in January 2003 that it would use the FlexIO and XDR technology in future game consoles in conjunction with the Cell microprocessor.
The FlexIO technology will be used to connect the various chips on a Cell-based motherboard, according to Rich Warmke, marketing director of the memory interface division at Rambus. A multicore Cell processor, by contrast, will use its own internal bus to connect multiple cores. However, 90 percent of the Cell's external pins are connected to either the FlexIO or XDR interfaces, evidence that the Cell's design emphasizes moving application and or 3D scene data around within main memory, Warmke said.
In total, the two interfaces combined can offer up to 100 Gbytes per second of total bandwidth, an order of magnitude above some other devices, Warmke said.
The FlexIO interface runs at 6.4-GHz, while the XDR interface runs at half of that speed, or 3.2-GHz. Warmke declined to offer specifics on the bandwidth mismatch. "We worked with Sony to understand their needs," he said. "With that application, that ratio of bandwidth was appropriate. Other applications may require more memory bandwidth and less chip-to-chip bandwidth."
Each 2.5x5.81mm SPE can issue two instructions per cycle to seven execution units using two pipelines. There is no out of order execution.
The FlexIO technology will be used to connect the various chips on a Cell-based motherboard, according to Rich Warmke, marketing director of the memory interface division at Rambus. A multicore Cell processor, by contrast, will use its own internal bus to connect multiple cores.
2.5MB of on Chip memory (512KB L2 and 8 * 256KB)
Some competitors, however, are skeptical that Cell will find much of a home outside of video games. One of the big problems with Cell, said Justin Rattner, an Intel Fellow, is that the processing units aren't identical, a situation that increases complexity and the opportunity for bugs.
"You've got this asymmetry," Rattner said. "It's like having two kinds of motors under the hood. We are very reluctant to adopt architectures like this because they take compatibility and throw it out the window."
ptzs disse:A presentação já deve ter acabado. Quando tiverem mais info avisem, tou acordado.
Xpirit disse:Acabaram de fazer uma demonstração. Correram o SuperPi em menos de 1s e o 3dmark falhou porque o cálculo do resultado deu out of range.
Amanhã já haverá scans dos papers e possívelmente os slides das apresentações. Novidades destas não acontecem todos os dias. A grande questão a seguir é: Bom, e o que fazer com isto? É a parte mais chata.
L1 cache has been replaced by 256K of locally addressable memory. The SPE's ISA, which is not VMX/Altivec-derivative (more on this below), includes instructions for using the DMA controller to move data between main memory and local storage. The end result is that each SPE is like a very small vector computer, with its own "CPU" and RAM.
This RAM functions in the role of the L1 cache, but the fact that it is under the explicit control of the programmer means that it can be simpler than an L1 cache. The burden of managing the cache has been moved into software, with the result that the cache design has been greatly simplified. There is no tag RAM to search on each access, no prefetch, and none of the other overhead that accompanies a normal L1 cache. The SPEs also move the burden of branch prediction and code scheduling into software, much like a VLIW design.
The individual SPUs can throw a lot overboard, because they rely on a regular, general-purpose ***** processor core to do all the normal kinds of computation that it takes to run regular code. The Cell system features eight of these SPUs all hanging off a central bus, with one 64-bit ***** core handling all of the regular computational chores. Thus all of the Cell 's "smarts" can reside either on the PPC core, while the SPUs just do the work that's assigned to them.
To sum up, IBM has sort of reapplied the RISC approach of throwing control logic overboard in exchange for a wider execution core and a larger storage area that's situated closer to the execution core. The difference is that instead of the compiler taking up the slack (as in RISC), a combination of the compiler, the programmer, some very smart scheduling software, and a general-purpose CPU doing the kind of scheduling and resource allocation work that the control logic used to do.
Xpirit disse:Só não acredito é nos 4-5Ghz de clock para o CELL em si. Os ***** 970FX vão em 2.5 Ghz. De 2.5 a 5 Ghz vai muito fruta.
O CELL talvez seja um Power a 2Ghz-2.5Ghz com 8 SPE's ao dobro da freq.
Tomorrow, after the next CELL session, I'll cover more of the Cell's basic architecture, including the mysterious 64-bit ***** core that forms the "brains" of this design.