Nemesis11
Power Member
http://www.corsairmicro.com/corsair/xms2.html
Artigo sobre DDR2:
http://www.tech-pc.co.uk/ddr2.php
Artigo sobre DDR2:
The trade off for this increase in bandwidth comes in the form of increased latencies, the number of clock cycles certain operations take to be carried out.
CAS (Column Address Strobe) latency, the number of cycles it takes for a column in memory to be selected, is expected to rise from 2 cycles as seen on current low latency modules and 3 cycles as used by very high bus speed DDR to most likely a minimum of 4 or 5 cycles for DDR-II. Similarly tRAS, the delay before being able to select a new row in memory, is likely to increase with 8 cycles looking to be the lowest it will be able to go, the same as is currently used on high speed DDR with some low latency DDR being able to run 5 cycles for tRAS.
http://www.tech-pc.co.uk/ddr2.php