Processador Curiosidades de hardware

[Nemesis11]

Isto já é algo antigo, mas aqui fica. É apenas um Business Card Computer que corre Linux.

As Specs é um Allwinner F1C100s (ARM9 + 32 MB RAM) e 8 MB Flash.

Custos em 2019:

Component	Price
F1C100s	$1.42
PCB	$0.80
8MB flash	$0.17
All other components	$0.49
Total	$2.88

https://www.thirtythreeforty.net/posts/2019/12/my-business-card-runs-linux/
https://www.thirtythreeforty.net/posts/2019/12/designing-my-linux-business-card/

 

[Nemesis11]

25 Kg de Aluminio + 2 Kg de Cobre.

Parte1
Parte2
Parte3

 

[godevskii]

Saía-lhe mais barato comprar uns tampões para os ouvidos

 

[Dark Kaeser]

https://twitter.com/i/web/status/1491079719521071112

Já o der8auer também tem estado a fazer artigos sobre os Power4/5, devem estar a substituir uns quantos de sistemas lá na Alemanha.

 

[JPgod]

A maquina do meio com aquele monte de slot de RAM madness!

 

[Nemesis11]

A maquina do meio com aquele monte de slot de RAM madness!

32 Slots
E metade é Optane ( 2 TB ).

 

[Nemesis11]

Apenas mais um MiniPC:

mmmmm:

Computador, Fonte e Placa Gráfica:

https://www.tomshardware.com/news/minisforum-b550-amd-ryzen-external-gpu

Não sei se terá grande sucesso, mas é uma curiosa variação para um GPU Externo.

 

[Dark Kaeser]

Intel Details Its Bitcoin-Mining 'Bonanza Mine' Chips and 3,600-Watt Miner​

At ISSCC 2022, Intel shared the deep-dive details of its new Bitcoin-mining Bonanza Mine ASICs and outlined how it melds 300 of these tiny power-efficient chips into a powerful 3,600W miner that delivers up to 40 THash/s of performance.

Here we can see the BMZ1 chip in its rather small 7 x 7.5mm exposed-die FCLGA package (132 balls). As you'll see below, 300 of these chips power the system.

Each chip die measures 4.14 x 3.42mm, for a total of 14.16mm^2 of silicon, so these are comparatively small slivers of silicon. The smaller die size improves yield and maximizes wafer area usage (up to 4,000 die per wafer), thus helping maximize production capacity (though it does require more wafer dicing/packaging capacity). Intel says these are 7nm ASICs, but doesn't specify if that is its own 'Intel 7,' the original 7nm before it renamed the process node to 'Intel 4,' or TSMC's 7nm process.

Each Bonanza Mine ASIC has 258 mining engines, and each engine computes parallel SHA256 double hashes. These engines comprise 90% of the die area and operate at what Intel characterizes as an 'ultra-low' voltage of 355mV.

Each ASIC operates at 1.35 to 1.6 GHz at 75C, consuming an average of 7.5W apiece while hitting up to 137 Ghash/s. That works out to 55 J/THash/s at 355mV.

Zooming out to the 300 chips in the system, there's a total of 4,248mm^2 of silicon that delivers up to 40TH/s at 3600W of power consumption. It's clear that Intel will need to be far more competitive against Bitmain and MicroBT's existing miners.

Intel solders on 75 Bonanza Mine ASICs per hash board, arranged in 25-deep voltage stacks with ganged stack-voltages. The hash board also houses a microcontroller that manages power-on and thermal/stack-voltage monitoring. A 10MB/s UART serial link shuffles data between the chips and the control unit that sits atop the full system

Here we can see both the block diagram and images of the full system. Four hash boards are placed vertically into a single unit with four fans that keep the system cool.

The control unit sits atop the device, housing an Intel-FPGA-based system controller and an Arm Cortex core that runs the mining daemon and distributes the work among the 300 chips. The ARM core also adjusts the on-die PLLs to control chip frequencies and verify the ASICs' hash results. As you would expect, the unit also has an Ethernet connection to communicate with a larger mining pool. The system also has a programmable power supply.

https://www.tomshardware.com/news/i...tm_source=twitter.com&utm_campaign=socialflow

Afinal na conferência o que eles apresentaram foi o BMZ1, o que eles anunciaram há dias, ainda sem data dfe lançamento, é o BMZ2.

 

[JPgod]

Impressiona e o tamanho do die... yields de 99,9%?

A board mais parece esta cheia de chips de memória...

 

[Dark Kaeser]

IBM Tellum, isto é um SoC da linha Z para Mainframes

ISSCC 2022: Design challenges of a new system and cache structure​

https://www-hardwareluxx-de.transla...sl=de&_x_tr_tl=en&_x_tr_hl=pt-PT&_x_tr_pto=sc

 

[Nemesis11]

No hardwareluxx. Capacitor Mod para passar um K6-2+ para K6-III+

https://www-hardwareluxx-de.transla...sl=de&_x_tr_tl=en&_x_tr_hl=pt-PT&_x_tr_pto=sc

Borlas de Hardware e mais de 1 minuto de ganho no Super Pi, só por ter o dobro da Cache L2. Bons tempos.


EDIT: Já agora, uns DIMMs para os Power:

https://www-hardwareluxx-de.transla...sl=de&_x_tr_tl=en&_x_tr_hl=pt-PT&_x_tr_pto=sc

 

[N3RO]

Não me recordava desta thread, vou partilhando umas coisas que me passem pelas mãos.

Meanwhile, do passado, alguém se lembra disto?

https://imgur.com/a/hgyP7ev

 

[Dark Kaeser]

O artigo da Hardwareluxx está em alemão, mas aquilo surgiu de um fórum que até está em Inglês, isto é a página 3
https://www.vogons.org/viewtopic.php?f=46&t=85071&start=40

onde surge o "famoso" Fritzchenz Fritz, o alemão que costuma tirar fotos de "die".
https://www.flickr.com/photos/130561288@N04/albums/72157715070825122

Entre os que tem na colecção estão agora também uns Elbrus 8S (um CPU russo com ISA própria e arquitectura VLIW-4 @tsmc 28nm)



https://www.flickr.com/photos/130561288@N04/albums/72177720295481227

Baikal (Arm v8.x russos @tsmc 28nm)



https://www.flickr.com/photos/130561288@N04/albums/72157719954545416

Também arranjou uma 3DFx Vodoo 3 ( @250nm )


https://www.flickr.com/photos/130561288@N04/albums/72157715138263437

e uma S3 Chrome S20 (@Fujitsu 90nm e chips de memória da Quimonda)


https://www.flickr.com/photos/130561288@N04/albums/72157720286723670

 

[Dark Kaeser]

A Graphcore apresentou um "novo" chip que eles chamam IPU, o Bow, que acho que é o primeiro a ser feito com o SoIC-WOW, se bem que que a 2ª wafer não tem qualquer "core" ou "uncore", serve apenas unicamente o propósito de alimentação e adiciona uns condensadores.

Graphcore BOW IPU Launched​

Each IPU sits four to an IPU Machine. In this case, it is the BOW-2000 IPU Machine.

https://www.servethehome.com/graphcore-bow-ipu-launched/

Graphcore Supercharges IPU with Wafer-on-Wafer​

Graphcore unveiled its third-generation intelligence processing unit (IPU), the first processor to be built using 3D wafer-on-wafer (WoW) technology.

Codenamed the Bow IPU, Graphcore’s new AI processor achieves up to 40% higher performance and 16% better power efficiency than the previous (non-WoW, but otherwise identical) product, launched in 2020.

The processor has the same 1472 independent processor cores and the same 900MB in-processor SRAM as the previous generation Colossus Mk2 IPU chip, but it runs around 40% faster than its predecessor – 1.85 GHz instead of 1.325 GHz – hence the up to 40% performance improvement.

Graphcore said its customers are seeing up to 40% increase in time to train across a range of models. Figures published by Graphcore show speedups of between 1.29x and 1.39x across a range of workloads including image classification (including vision transformers), object detection, text to image, graph networks, natural language processing, and speech recognition.

Power efficiency (performance per watt) also improved between 9-16% across a smaller range of workloads, according to Graphcore’s figures.

WoW factor

Graphcore is TSMC’s lead customer for the foundry’s wafer-on-wafer (WoW) technology.

WoW chips feature two wafers bonded together: a wafer of processor die, and a wafer of power delivery die. The power delivery wafer contains deep trench capacitors, similar to those used to store information in DRAM, used as a charge reservoir and connected to the transistors on the processor die at very low impedance.

“This allows the transistors to operate much more quickly at good power efficiency, so the net effect on the Bow IPU processor is to increase its clock speed,” said Graphcore CTO Simon Knowles, despite using the same processor design and the same process technology (TSMC 7nm) for the processor die.

WoW depends on two key technologies.

Hybrid bonding allows two wafers to be bonded together, metal sides together, without any interstitial bumps.

“It’s like a kind of cold weld,” said Knowles. “The advantage of doing it this way is an extremely high density of interconnect between the wafers.”

The other key technology is a new type of through-silicon via (TSV) called a back-side TSV (BTSV) which allows connection to layers inside the wafer “sandwich.”

WoW is distinct from chip-on-wafer technologies used in the industry to mount memory die on top of processor die; Knowles said the differences result in finer connection pitch for WoW, though he did not reveal what the pitch is. Knowles ascribed the finer pitch to the ease of aligning two complete wafers rather than two individual die, and the ability to use an ion etch process for BTSVs due to the power delivery wafer being extremely thin. The thin wafer, “thinner than cling film,” is so thin that it’s transparent and floppy, so bonding to the thicker wafer before thinning allows the thicker wafer to act as a mechanical support during subsequent process steps. This wouldn’t be possible with individual die, he said.

“We’ve been working With TSMC as their vanguard customer in this technology for about two years now,” said Knowles. “An enormous amount of work has been done to make this a production technology, and I’m sure any of our rivals who are starting today will take a good long time to get to where we are.”

https://www.eetimes.com/graphcore-s...tter&utm_medium=social&utm_campaign=Articles#

Graphcore Announces World’s First 3D Wafer On Wafer Hybrid Bond Processor​

Graphcore achieved this by implementing a large number of deep trench capacitors on a second wafer and using TSMC’s SoIC wafer-on-wafer hybrid bonding technology to integrate the two. Most designs include some deep trench capacitors on die or even on package, but this is the first instance of 3D hybrid bonding for them. These embedded deep trench capacitors are similar to those found in prior DRAM processes. The packaging innovations enable orders of magnitude more deep trench capacitor capacity than any other high performance leading edge chip has had in the past.

These capacitors sit on the base die and smooth the power delivery and increase stability by reducing the size of transient spikes. In laymen's terms capacitors are for energy storage. When the chip's current draw rapidly changes, they reduce voltage droop and smooth out the power delivery. The actual science behind it is more complex of course.

Graphcore is TSMC’s vanguard customer for this technology. The hybrid bonding process here is wafer-on-wafer rather than chip-on-wafer. This provides a huge benefit to density of packaging. AMD’s 3D V-Cache technology uses TSMC’s chip-on-wafer bonding at a 17-micron pitch for TSV’s. The wafer-on-wafer hybrid bonding technology is able to offer TSV’s at 1/10th the pitch. In other words, in the area that chip-on-wafer hybrid bonding is able to offer 100 TSVs, the wafer-on-wafer technology can offer 10,000.

https://semianalysis.substack.com/p/graphcore-announces-worlds-first?s=r

https://twitter.com/i/web/status/1499323803083624448

Basicamente este BOW, é o mesmo "die" do Colossus MK2, ao qual é acresecentada uma outra wafer para "alimentação", e isso é feito ao nível da wafer (300mm de diâmetro) e não a cada chip individualmente como no caso do AMD V-cache, só depois de a wafer finalizada é que os chips são individualmente cortados.

Como só dá para testar os chips individualmente depois de cortados da wafer, para manter os yields aparentemente o chip foi desenhado com alguma redundância, o que naturalmente aumenta a área do mesmo.

 

[JPgod]

O Linus comprou o stock perdido de uma loja que faliu e man... é literalmente voltar no tempo

Coolers de HDD, HDD backplanes, coolers para ATI 4850 e NVIDIA 8800 GT e outras coisas bizarras como um alarme se a fan do cpu morrer

a única coisa que se aproveita hoje é um cooler de memória

Olhando a tralha de storage e afins e hoje olhas para um M.2 = magia negra

Ter um PC só com isso e pensar no passado os grandes blocos de alumínio que se tinha...

 

[Dark Kaeser]

Intel Gaudi HL2000 (ex-Habana Labs)

https://twitter.com/i/web/status/1505510910466658308

Aparentemente há 2 modelos

https://videocardz.com/newz/intel-h...ed-features-6-stacks-of-high-bandwidth-memory

 

[Nemesis11]

Apenas uns Selos (Um pouco mais pequenos que os do post anterior )

https://github.com/solderparty/rp2040_stamp_hw

https://www.adafruit.com/product/4900

Um processador com um aspecto um pouco diferente do normal. Samsung Alpha 21264B Proto.

http://www.chipdb.org/img-samsung-alpha-21264b-proto-6020.htm

"Pregnancy Test Doom".

https://twitter.com/i/web/status/1302820468819288066

 

[Dark Kaeser]

cada um usa o que tem mais à mão, penso eu de que

https://twitter.com/i/web/status/1506049246016987143

https://twitter.com/i/web/status/1507494952326119427

 

[Nemesis11]

cada um usa o que tem mais à mão, penso eu de que

Essa conta de twitter tem mesmo muito hardware fora do comum, a maioria da Via

Quad CPU Via Eden (WTF!!!!! ):

Placa de rede da Intel com um Chipset(?):

Via C7 com Northbridge e iGPU integrado:

Dual Via Nano X2:

Dual Via CNS:

Board da Zhaoxin:

Muito interessante.

 

[Dark Kaeser]

Sim, não faço ideia onde ele arranja isso tudo, até porque algumas delas são engineering samples, usadas para testes iniciais aos cpu, etc...