The DDR memory interface appears to wrap around both L2 caches, meaning that it looks like both cores have their own 128-bit memory interface; whether or not both memory controllers will be enabled is another thing, but if this is true we have a number of implications to talk about.
If dual core Opterons do indeed have two memory controllers, the pincount of dual core Opterons will go up significantly - it will also make them incompatible with current sockets. AMD is all about maintaining socket compatibility so it is quite possible that they could only leave half of the memory controllers enabled, in order to offer Socket-940 dual core Opterons. AMD isn't being very specific in terms of implementation details, but these are just some of the options.
AMD did mention that they will eventually start referring to Opteron server configurations according to the number of sockets, not CPUs, the platform is capable of supporting. For example, a 1 socket Opteron server could either be a 1-way or a 2-way configuration, depending on whether a single or dual core Opteron is used.
