EU Signs Declaration for 2 nm Node and Custom Processor Development

[muddymind]

European Union has today processed a declaration that was signed by 17 member states about the development of a 2 nm semiconductor node and an advanced low-power processor. The declaration signed today proposes that the EU puts away 145 billion Euros for the development of the technologies needed to manufacture a 2 nm semiconductor manufacturing process, along with the development of a custom, low-power embedded processor designed for industrial applications. The 17 member countries include Belgium, France, Germany, Croatia, Estonia, Italy, Greece, Malta, Spain, The Netherlands, Portugal, Austria, Slovenia, Slovakia, Romania, Finland, and Cyprus. All of the countries listed are going to join the development of these technologies and will have the funds to do it over the next 2-3 years.

EU Declaration

To ensure Europe's technology sovereignty and competitiveness, as well as our capacity to address key environmental and societal challenges and new emerging mass markets, we need to strengthen Europe's capacity to develop the next generation of processors and semiconductors. This includes chips and embedded systems that offer the best performance for specific applications across a wide range of sectors as well as leading-edge manufacturing progressively advancing towards 2 nm nodes for processor technology. Using connectivity, where Europe enjoys global lead, as a major use case driver for developing such capacity enables Europe to set the right level of ambition. This will require a collective effort to pool investment and to coordinate actions, by both public and private stakeholders.

https://www.techpowerup.com/276539/...or-2-nm-node-and-custom-processor-development

 

[Camões]

Gostei desta, já não era sem tempo!

 

[Torak]

Creio que isto será mais importante para sistemas industriais e militares, do que para produtos de consumo.
Não me parece que vamos ver chips de 2nm feitos na EU nos nossos PCs e consolas.

BTW, até admira ver Portugal pelo meio.
Se calhar precisavam de alguém para levar umas bifanas e uns garrafões de tinto

 

[Dark Kaeser]

Não é por nada, mas não é por falta de R&D, esse existe.

Há é falta de empresas que que tenham produtos para serem fabricados e "foundries" que precisem desses processos avançados.

- IMEC (Leuven, Bélgica)
https://www.imec-int.com/en/about-us#about

- CEA-Leti (Grenoble, França)
https://www.leti-cea.com/cea-tech/leti/english/Pages/Leti/About-Leti/about-leti.aspx

Falta é passar a parte de pesquisa para a parte dos produtos, e isso não é na maioria dos casos feito na Europa.

- Scaling CMOS beyond FinFETs: from nanosheets and forksheets to CFETs

Julien Ryckaert, program director 3D hybrid scaling at imec, sketches out an evolutionary path towards 2nm and beyond technology nodes. Along this exciting road, he introduces the nanosheet transistor, the forksheet device and the CFET. Part of these insights have been presented at the 2019 IEEE International Electron Devices Meeting (IEDM).

https://www.imec-int.com/en/imec-ma...nfets-from-nanosheets-and-forksheets-to-cfets

- A view on the logic technology roadmap
Advancing the front-end, back-end and middle-of-line towards the 1nm technology generation

While chipmakers are moving ahead with technology generations, maintaining the same timeline for scaling transistors in the front-end-of-line (FEOL), contacts and interconnects in the middle- (MOL) and back-end-of-line (BEOL) has become challenging. In this article, Naoto Horiguchi, director CMOS device technology, and Zsolt Tokei, program director nano-interconnects at imec have pooled their expertise to present a joint technology roadmap. Along the scaling path, they introduce new device architectures in the FEOL, and novel materials and integration schemes in the MOL and BEOL. They discuss the status, challenges and rationale behind the various options – which offer the chip industry a possible path towards the 1nm technology generation.

https://www.imec-int.com/en/articles/view-logic-technology-roadmap

-

CEA-Leti today announced a new collaboration with Intel on advanced 3D and packaging technologies for processors to advance chip design. The research will focus on assembly of smaller chiplets, optimizing interconnection technologies between the different elements of microprocessors, and on new bonding and stacking technologies for3D ICs, especially for making high performance computing (HPC) applications.

https://www.leti-cea.com/cea-tech/l...h-Cutting-Edge-3D-Packaging-Technologies.aspx

- CEA Institutes Combine 3D Integration Technologies & Many-Core Architectures to Enable High-Performance Processors That Will Power Exascale Computing

• The CEA technologies presented in the paper are powering demonstrators in the ExaNoDe and INTACT projects, which havedeveloped integrated prototypes with technology building blocks to support the EU's drive towards exascale computing. The two institutes combined CEA-Leti's expertise in silicon and 3D sequential integration with CEA-List's many-core architectures, which are differentiated by their high level of scalability and power efficiency. They have demonstrated the benefit of new integration methods and processes following two main paths: finer 3D interconnect pitches, leading to improved bandwidth between compute chiplets, and assembly technologies that allow increasing heterogeneity in packaging, which improves peak performance.

https://www.leti-cea.com/cea-tech/l...es-to-Enable-High-Performance-Processors.aspx

Basta pensar que a maior empresa europeia de semicondutores é a Infineon, que tem várias foundries, nenhuma das quais recorre a processos recentes, e a 2ª é a ST-Micro, cujo processo mais recente é 28nm...

https://www.icinsights.com/files/images/bulletin20201123Fig01.png

 

[Camões]

Eu acho esta iniciativa tão ou mais importante que outras conjuntas como o programa espacial europeu ou o acelerador de partículas. Trata-se de arranjar "massa critica" em sectores de ponta que depois suportam ou desenvolvem outros sectores subsidiários ou de alguma forma ligados. Se a Europa no seu conjunto não tiver programas destes não só perderá relevância como os seus recursos financeiros servirão apenas para serem aplicados noutras regiões do globo mais apetecíveis. Aplaudo com as 2 mãos e espero que tenhamos o bom senso de contribuir com mais inteligência que dinheiro. A nossa juventude precisa de projectos aliciantes e aqui está uma possibilidade.

 

[Dark Kaeser]

University of Copenhagen and CEA-Leti Collaboration Leads to Quantum Computing Milestone

The French company Leti makes giant wafers full of devices, and, after measuring, researchers at the Niels Bohr Institute, University of Copenhagen, have found these industrially produced devices to be suitable as a qubit platform capable of moving to the second dimension, a significant step for a working quantum computer.

The importance of industry scale production

Assistant Professor at Center for Quantum Devices, NBI, Anasua Chatterjee adds: “The original idea was to make an array of spin qubits, get down to single electrons and become able to control them and move them around. In that sense it is really great that Leti was able to deliver the samples we have used, which in turn made it possible for us to attain this result. A lot of credit goes to the pan-European project consortium, and generous funding from the EU, helping us to slowly move from the level of a single quantum dot with a single electron to having two electrons, and now moving on to the two dimensional arrays. Two dimensional arrays is a really big goal, because that’s beginning to look like something you absolutely need to build a quantum computer. So Leti has been involved with a series of projects over the years, which have all contributed to this result.”

https://www.hpcwire.com/off-the-wir...oration-leads-to-quantum-computing-milestone/

 

[Dark Kaeser]

IEDM 2020 – Imec Plenary talk

The Imec roadmap is for 3nm logic nodes to have 44-48nm Contacted Poly Pitch (CPP) and 21-24nm Minimum Metal Pitches (MMP), the 2nm logic node to be 40-44nm CPP and 18-21nm MMP and the 1.5nm logic node to be 40-44nm CPP, and 18-21nm MMP. I expect TSMC to be make risk starts with a 3nm node in late 2021 and production in 2022 and the CPP and MMP to be in the range of the numbers Imec proposes. I expect TSMC’s 2nm node to make risk starts in 2023 and production in 2024 and once again to have CPP and MMP values in the range that Imec presented. For 1.5nm Imec does not show any reduction in CPP and MMP ranges presumably reflecting a change to stacked transistors (more on this later) as a technique to drive density.

https://semiwiki.com/events/294432-iedm-2020-imec-plenary-talk/