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Hynix Receives Intel Validation For Low Latency High Performance 512Mb DDR2

Discussão em 'Novidades Hardware PC' iniciada por redalert, 18 de Janeiro de 2004. (Respostas: 10; Visualizações: 1044)

  1. redalert

    redalert Folding Member

    "Hynix Receives Intel Validation For Low Latency High Performance 512Mb DDR2

    San Jose, California, December 15, 2003 - Hynix Semiconductor Inc., today announced its low latency high performance 512Mb DDR2 components have successfully passed Intel validation with mass production scheduled for first quarter of 2004. Hynix is also currently sampling its 1Gb DDR2 components and it is expects to pass Intel validation by end of this year.

    Hynix has received validation on its low latency 512Mb DDR2-533 (CL-tRCD-tRP/4-4-4) and DDR2-400 (CL-tRCD-tRP/3-3-3) in x8 configuration. The Hynix 512Mb DDR2 SDRAM fully complies with JEDEC DDR2 specifications and standards and are manufactured on the company’s advanced Golden Chip .11-micron process technology. The devices can operate at a data transfer rate of up to 800 Mbps (Megabits Per Second) at 1.8V and are available in x 4/x8/x16 configurations in a FBGA package.

    Hynix anticipates strong demand for DDR2 memory products in 2004 as the server and PC industry adopt various Intel chipsets supporting DDR2. According to Farhad Tabrizi, Vice President of Worldwide Marketing, “This Intel validation further reflects Hynix’s strength and leadership position in next generation memory architecture.”

    "


    http://www.hynix.com/allnews/eng/memeng_read.jsp?NEWS_DATE=2003-12-17:16:18:21&CurrentPageNo=1


    mais um fabricante pras ddr2... :D



    vamos la ver o k sai daki..

    serao mais "umas rimms" pa ficar nas prateleiras das lojas?!?..
     
  2. SKATAN

    SKATAN Power Member

    "Hynix has received validation on its low latency 512Mb DDR2-533 (CL-tRCD-tRP/4-4-4)"



    4/4/4 é low latency em DDR2 ?:rolleyes:
     
  3. |Oc|CRASH_OVer

    |Oc|CRASH_OVer Suspenso

    tava a pensar isso...... tb reparei nos 1.8v
     
  4. fallenhaven

    fallenhaven I'm cool cuz I Fold

    nunca me lembro de ter visto CAS 4 num modulo de memorias... nem numa bios... sobretudo numa bios :P
     
  5. |Oc|CRASH_OVer

    |Oc|CRASH_OVer Suspenso

    nforce2 podes escolher de CAS 2 até 7....
     
  6. fallenhaven

    fallenhaven I'm cool cuz I Fold

    n kerendo ser chato... mas tens a certeza? eu tive uma RDA3+ a bem pouco tempo e so tinha CAS 2 - 2,5 e 3.... as Via ainda costumavam ter CAS 1,5 , mas acho que raramente funcionava...
     
  7. Crusher

    Crusher Power Member

    Pelo que sei DDR2 em ram de sistema em performance é

    DDR2=1,5xDDR

    Acho que o DDR2 que vai ser usado nestes sistemas não é bem igual ao das gráficas.


    Just my 0.0000000000002€
     
  8. |Oc|CRASH_OVer

    |Oc|CRASH_OVer Suspenso

    fallenhaven
    de facto, CAS é só aquele timming entre 1.5 e 3.... os outros é que vao de 2 a 7 e um outro a mais ainda....
     
  9. iJFerreira

    iJFerreira Banido

    CAS 2 @ 100 Mhz = CAS 4 @ 200Mhz.

    CAS = Tempo de acesso a uma coluna de dados / Periodo do clock

    Quanto maior for a freq do clock (1/periodo) menor é o período
    logo para o mesmo tempo de acesso o CAS é maior.
     
  10. |Oc|CRASH_OVer

    |Oc|CRASH_OVer Suspenso

    ya eu vi no google.... many, many time ago.... in a far, far way galaxy!
     
  11. fallenhaven

    fallenhaven I'm cool cuz I Fold

    o que vai mais acima pode atingir valores ate 15 é o tRAS se nao estou em erro, e teoricamente o ideal seria tRAS = CAS + TRCD + 2, para evitar q o precharge corte ciclos de memoria validos

    from mushkin site:

    "Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers).

    Any tRAS setting lower tRCD + CAS + 2 cycles will allow the memory controller to close the page “in your face!” over and again and that will cause a performance hit because of a truncated transfer that needs to be repeated. "

    agora a verdade e que um sistema com uma nf7-s fica mais rapida a 2-2-2-11 :D
     

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