Processador Intel Meteor Lake [2023]

muddymind

1st Folding then Sex
We already got some details from Intel such as the fact that Intel's Meteor Lake line of desktop and mobility CPUs are expected to be based on a new line of Cove core architecture. This is rumored to be known as the 'Redwood Cove' and will be based on a 7nm EUV process node. It is stated that the Redwood Cove is designed from the ground up to be an agnostic node which means that it can be fabricated at different fabs. There are references mentioned that point out to TSMC to be a backup or even a partial supplier for the Redwood Cove-based chips. This might tell us why Intel is stating multiple manufacturing processes for the CPU family.



The Meteor Lake CPUs may possibly be the first CPU generation from Intel to say farewell to the ring bus interconnect architecture. There are also rumors that Meteor Lake could be a fully 3D-Stacked design and could utilize an I/O die sourced from an external fab (TSMC sighted again). It is highlighted that Intel will be officially utilizing its Foveros Packaging Technology on the CPU to inter-connect the various dies on the chip (XPU). This also aligns with Intel referring to each tile on 14th Gen chips individually (Compute Tile = CPU Cores).

The Meteor Lake Desktop CPU family is expected to retain support on the LGA 1700 socket which is the same socket used by Alder Lake & Raptor Lake processors. We can expect DDR5 memory and PCIe Gen 5.0 support. The platform will support both DDR5 & DDR4 memory with the mainstream and budget tier options going for DDR4 memory DIMMs while the premium & high-end offerings going for DDR5 DIMMs. The site also lists down both Meteor Lake P and Meteor Lake M CPUs that will be aimed at mobility platforms.

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Intel Achieves Power-On For Next-Gen Meteor Lake CPU Compute Tile, Delivers Outstanding Performance According To CEO


Intel Achieves Power-On For Next-Gen Meteor Lake CPU Compute Tile, Delivers Outstanding Performance According To CEO
Intel reported earlier this week that the company was successful in powering a single compute tile of its next-gen Meteor Lake CPUs. Back in March, Intel taped in the first 7nm Compute Tile so this marks another milestone in the development of Intel's next-generation x86 architecture and CPU family.

Intel Meteor Lake Compute Tile Achieves Power-On, CPU Delivers Outstanding Performance 'Right Where We Expected', Says CEO​

Meteor Lake is Intel's 14th generation Core processor that is expected to release in 2023. The chip itself utilizes innovative technology with its Intel 4 (7nm) manufacturing process. Intel's testing was said to be successful and on target with their current fabrication plans, especially for almost two years ahead of release showing actual computational power.

"On Intel 4, we had taped out our compute tile for Meteor Lake and this quarter it came out of the fab and powered up within 30 minutes with outstanding performance, right where we expected it to be. All told, this is one of the best lead product startups we have seen in recent memory, which speaks to the health of the process."
—Pat Gelsinger, Intel CEO, during the company's earnings call that was held this week

For Intel, this breakthrough with their Meteor Lake processor is a new step towards the possibility of witnessing silicon chips processing information and being extremely stable. However, the concept does raise pessimism of whether it will provide above expected performance or even remain stable. Eventually, developers will be expected to alter as well as provide additional parts and technology to Meteor Lake. The largest hurdle right now is the cost of manufacturing, especially in this case with the current chip shortage and high cost of parts and devices.
 
O diagrama lógico tem compute die, SoC die (estilo IOD da amd) e gpu die. Isso são 3 mas nas fotos vê-se claramente 4 dies. Não sei o que é a 4a.
 
Podem ser muitas coisas, cache, die de teste já que são amostras de engenharia... Mas talvez o que faça mais sentido é talvez IPU+VPU ou algum tipo de neural engine
 
A Intel tem sido tão transparente com este produto, que seria uma surpresa aquele 4º tile seja algo de muito importante. Também não sei bem o que poderiam colocar naquele 4º tile. Talvez Cache, ou algum tipo de IO (Thunderbolt, Wireless, etc).
Também é possível que não seja nada e esteja ali só por uma questão mecânica.

EDIT: Die Shot do Compute die.
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E a possível interpretação, em que tem 2 P Cores e 8 E Cores.
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https://www.comptoir-hardware.com/a...-un-die-shot-de-meteor-lake-ca-vous-dit-.html
 
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Sera tipo um chip de trust ? Tinha visto algum tempo que a intel andava a desenvolver um chip de trust por causa das falhas de segurança que os cpus tinham se é ou não, não sei mas que faz algum sentido faz :P
 
Deves estar a pensar no Microsoft Pluton e no mundo PC, em soluções já existentes há muitos anos, como o Intel ME, AMD FSP, etc, são microcontroladores extremamente pequenos, que estão embedded no próprio CPU ou no Chipset. Os Ryzen 6000 já têm aquele Microsoft Pluton e também se encontra embedded no SOC.
A Apple tem o T2, que é um chip externo ao SOC:
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Há essa possibilidade daquela die ser para essa finalidade, mas acho que é pouco provável.
 
Aparentemente IO Die...

Meteor Lake Die Shot and Architecture Analysis – Why Is Intel 4 Only A 40% Area Reduction Versus Intel 7?​


Using the first party and media images of the Meteor Lake wafer, packages, and video of the packaging process, we can determine the various die sizes of the chiplets used by Intel on Meteor Lake. The compute tile, which is comprised of various CPU core tiles as well as some of the associated fabric, is only a mere ~40mm2.
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The other dies measure in at ~174mm2, ~10mm2, ~95mm2, and ~23mm2. The exact purpose of each of these dies is not confirmed, but we believe we believe they are for IO, SOC, and GPU. We will dive into each of these in their own section later in this article. First, let’s talk about the compute tile.
https://semianalysis.substack.com/p/meteor-lake-die-shot-and-architecture?s=r
 
De notar que ~40mm2 é com uma die com 2 P Cores e 8 E Cores. Uma versão desktop provavelmente terá 4 destas dies, digo eu.

Já agora, para quem se questiona o que é aquela "SOC die" e porque tem aquele tamanho:
We believe the SOC tile is a combination of IP that is on the existing CPU die as well as the PCH. With Meteor Lake, there is no PCH/chipset. Currently PCH’s are built on a 14nm class process node as a way to reduce cost for additional IP. The PCH on Alder Lake mobile is 54mm2 and contains IP such as the IO needed for more PCIe lanes, USB ports, SATA, Intel Management Engine, and the digital logic needed for Wi-Fi. We believe all of this will also be included on the SOC tile. Furthermore, there is a variety of other logic currently on the CPU that could be moved there. The whole uncore area on the left side on Alder Lake P (TB4, Display PHYs, PCIe PHY, digital control logic, Image Processing Unit, GNA AI Accelerator, System Agent and Memory Controller) takes 55.9mm². The majority of this IP will be moved to the SOC tile, with some IP being moved to the 10mm² IO tile.

In total, we believe this is 54mm2 of 14nm and ~40mm2 of uncore Intel 7 silicon will be consolidated to the SOC die. There will be some redundant area on the chipset, but given Intel likely enhances some of these IP blocks. All of this IP would fits nicely within the measured ~94.9mm2 of the SOC tile even if it is on a somewhat older node. We believe Intel will use a 14nm or 16nm class node here again, but there have been some rumors that they may utilize a TSMC N6 node for this tile.
Ainda só vi na diagonal o artigo, mas parece bem interessante. Também tem uma versão video:
 
Bom o SoC é o maior die, e pensava que seria o GPU...

Mas ponto isso tem a função do chipset + boa parte do IO de um CPU atual
 
Bom o SoC é o maior die, e pensava que seria o GPU...
O GPU die usa TSMC 3 nm e eles dizem que têm confirmação disso, enquanto o SOC die parece que deverá usar 14 ou 16 nm, apesar de eles colocarem a possibilidade de usar TSMC 6 nm.
Se usar 14/16, parece-me normal aquela área no SOC die.

Já agora, eles pensam que aquele GPU die terá 64 ou 96 EUs.
Com este valor consegue-se perceber +/- que área terá um GPU maior, com 192, 256, 512, etc EUs, a 3 nm TSMC.
Mas essa é a parte "estranha": se boa parte do IO foi movido para o SoC die, o que raio é vai estar no IO die/tile?
Vai estar............IO. :D

Eles colocam duas possibilidades para o que está naquela IO die. Controladores de memória ou Thunderbolt+Display Engines.
Se eles estiverem correctos e existirem duas IO dies, acho que a explicação é simples. Usarem diferentes processos de fabrico nas 2 IO dies.
 
Se for 14nm então explica o tamanho, se for 6nm é o que raio tem ai dentro para ser tão grande...

A IO die do zen4 é TSMC 6nm, terá 120mm2 (pouco menor que a do zen2/3 @ 12/14nm), mas vai ter o GPU + displayoutput + decode e vídeo e tudo associado lá dentro, se calhar se fosse sem GPU, teria uns 50-60mm quanto muito. E ainda é algo complexo com 2 links IF, controlador DDR5 128 bits, 28 lanes pcie + usbs + sabe se lá o que.
 
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