Processador Intel Sapphire Rapids (2022 - SR-SP e SR-X)

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Pelo vistos este leak do "Roadmap" bate certo com os rumores que já havia. Este Sapphire Rapids terá versões para o mercado servidores SP e high end Desktop X.

Intel Sapphire Rapids to feature up to 56 cores, 350W TDP and 64GB of HBM2 memory​


Intel-Xeon-Sapphire-Rapids-Specifications-1200x633.jpg


Sapphire Rapids features 10nm Enhanced SuperFin architecture and it will be offered for both servers (Sapphire Rapids-SP) and high-end desktops (Sapphire Rapids-X). Not much is known about the latter, other than we have heard that the motherboards for the next X-series are already being samples.

Para além dos aumentos e da DDR5, CXL e PCIe-5, a maior novidade será mesmo a possibilidade de ter HBM2e

The slide confirms that Sapphire Rapids is now planned up to 56 cores and it will scale from one to eight sockets, just as Cascade Lake. We also have confirmation on the maximum TDP of 350W. This was long speculated and has already appeared in other leaks (see below). It’s a 100W power increase over Cooper Lake and 70W more than just released Ice Lake-SP.

Intel 4th Gen Xeon Scalable will support DDR5 up to 4800 MHz (1 DIMM per channel). The platform will support up to 80 PCI Express lanes. According to the slide, the CPUs will support PCI Gen5 x16, x8, x4, and PCI Gen4 x2. Unlike the previous Xeon CPUs series, Sapphire Rapids will introduce on-package 64GB HBM2 memory with bandwidth up to 1 TB/s per socket.

já havia sido também verificado por um outro twitteiro o TDP das diferentes configurações

Intel-Sapphire-Rapids-Info.jpg


This list confirms that the top 56 core SKU will have a TDP of 350W, but it also extends on this information by providing TDP for 44 core (270W) and 24 core variants (225W).
https://videocardz.com/newz/intel-s...-to-56-cores-350w-tdp-and-64gb-of-hbm2-memory

De resto de uma outra fonte:



 
Ainda relacionado com o Ice lake-SP, no ultimo link.

for starters, the turbo, a massive regression over cascade/cooper, but thats not the cursed part, notice how 8380, the top SKU has one of the lowest turbos of the whole lineup? and how lower core counts get better clocks?

well, this is because intel has to allow very crappy cores to be able to make a 40C(and dont expect any real volume anyways), and since ST turbo has to be done by all cores, well, you get this cursed stack where higher SKUs clock less

this CPU has also the record on most steppings in a final CPU, with final being D2, yes 4 big revisions and god knows how many small ones

this and the >2 year delay have all the same root cause: 10nm+, which could have been avoided by doing TGL SP or porting this to 10nm++ anyways so many steppings and node refinements make this 10nm+ variant, 10nm+v2 able to "yield" such a huge die...

different arch, but yes, its similar, funny how TGL SP got replaced by SPR but would have launched same or earlier than ice...

Isto mostra bem o pesadelo que deve ter sido o desenvolvimento deste CPU. Havia quem dissesse que o melhor era a Intel ter cancelado o Ice Lake-SP.
Acho que por todas as razões, o Ice Lake-SP é o fim de uma era para a Intel e do lado do cliente, é melhor evitar.

Este Sapphire Rapids, com 56 Cores, irá competir com o Epyc Zen4, que parece que irá ter 96 Cores. No entanto, irá usar o Golden Cove, que ainda deve ser melhor que o Core que está no Tiger Lake. Ao mesmo tempo, irá usar Tiles e parece ser um monstro a nível de IO, com HBM, DDR5 e 80 lanes Pci-Ex Gen5.

Espero que seja o relançar "real" dos produtos para Servidores, da Intel. Quem sabe, até poderá aparecer uma variante para o mercado HEDT. :)
 
Parece confirmar-se a utilização de HBM do leak, será apenas para segmentos específicos

Linux Kernel Prepares For Intel Xeon CPUs With On-Package HBM Memory
The i20nm EDAC driver for error detection and correction reporting has been extended for supporting future Xeon CPUs with onboard HBM memory.

The patches do spell out quite clearly, "On package memory is coming (in the future)...A future Xeon processor will include in-package HBM (high bandwidth memory). The in-package HBM memory controller shares the same architecture with the regular DDR memory controller. Add the HBM memory controller devices for EDAC support."

So far all indications are that on-package HBM memory will be found in select Xeon Sapphire Rapids SKUs.
https://www.phoronix.com/scan.php?page=news_item&px=Linux-Prepares-Xeon-HBM
 
A Intel já fez uma "apresentação"

Intel to Launch Next-Gen Sapphire Rapids Xeon with High Bandwidth Memory​


As part of today’s International Supercomputing 2021 (ISC) announcements, Intel is showcasing that it will be launching a version of its upcoming Sapphire Rapids (SPR) Xeon Scalable processor with high-bandwidth memory (HBM). This version of SPR-HBM will come later in 2022, after the main launch of Sapphire Rapids, and Intel has stated that it will be part of its general availability offering to all, rather than a vendor-specific implementation.

PDF%20%20Final%20Intel%20ISC%20June%2018%20Deck%20for%20Press%20Briefing%20-page-017_575px.jpg


Sapphire Rapids: What We Know​

Intel has been teasing Sapphire Rapids for almost two years as the successor to its Ice Lake Xeon Scalable family of processors. Built on 10nm Enhanced SuperFin, SPR will be Intel’s first processors to use DDR5 memory, have PCIe 5 connectivity, and support CXL 1.1 for next-generation connections. Also on memory, Intel has stated that Sapphire Rapids will support Crow Pass, the next generation of Intel Optane memory.

For core technology, Intel (re)confirmed that Sapphire Rapids will be using Golden Cove cores as part of its design. Golden Cove will be central to Intel's Alder Lake consumer processor later this year, however Intel was quick to point out that Sapphire Rapids will offer a ‘server-optimized’ configuration of the core.
https://www.anandtech.com/show/1679...al&utm_source=twitter&utm_campaign=socialflow
 

PR News....​

  • June 29, 2021
Updates on Intel’s Next-Gen Data Center Platform, Sapphire Rapids
Lisa Spelman
Corporate Vice President, General Manager of the Xeon and Memory Group
parte a reter do comunicado
Given the breadth of enhancements in Sapphire Rapids, we are incorporating additional validation time prior to the production release, which will streamline the deployment process for our customers and partners. Based on this, we now expect Sapphire Rapids to be in production in the first quarter of 2022, with ramp beginning in the second quarter of 2022.
https://www.intel.com/content/www/u...enter-platform-sapphire-rapids.html#gs.4k2auq

Não sei se é só impressão minha, mas

TovM.gif
 
Finalmente apareceu um produto para o mercado HEDT, por parte da Intel.
l5QFyBE.jpg


https://videocardz.com/newz/intel-sapphire-rapids-hedt-appears-in-a-roadmap-with-w790-chipset

No Roadmap, aparece com o Chipset W790. Também aparece a meio do próximo ano, mas ainda agora anunciaram um atraso para a versão Servidor, por isso, pode chegar mais tarde do que está neste Roadmap.
Seja como for, é bom sinal a Intel sentir-se confiante em lançar um produto para este mercado.
 

NNSA Selects Dell for $40M CTS-2 Commodity Computing Contract​


The labs are opting for primarily straight x86 gear, powered by the forthcoming ‘Intel 7’ Sapphire Rapids CPU and – when it becomes available – the high-bandwidth memory (HBM) version of said CPU. The Dell PowerEdge systems will be installed beginning in mid-2022 with deliveries continuing through 2025.
With the timing of the first installations planned for mid-2022, CTS-2 procurement lead Matt Leininger told HPCwire that the initial systems will leverage Intel Sapphire Rapids CPUs with DDR5. He expects systems with the HBM Sapphire Rapids parts will come after that, subject to availability and the timing needs of the three labs.

“We expect that there’ll be several orders that will be CPU plus HBM systems (no DDR5),” said Leininger, deputy for advanced technology projects at Lawrence Livermore National Laboratory. “There’s a lot of interest [in those HBM CPUs], and those decisions are being made now.”
https://www.hpcwire.com/2021/09/28/nnsa-selects-dell-for-40m-cts-2-commodity-computing-contract/
 
E bom que a AMD meta o Chagall já com 3Dcache, que o Shappire Rapids vai destruir totalmente, então com HBM2, ate um 48C deve limpar os 64C
 
Já tinha visto a imagem e malta a estranhar que os tiles aí são rectangulares enquanto que tudo o que tinha sido visto e mostrado até agora eram sempre quadrados. Se isso for confirmado então vai ser completamente silício distinto e não vão rentabilizar o mesmo design entre produtos como a AMD bem tem aproveitado.

Edit: já para não falar que devido ao meshing entre cores, MMU e IO na periferia vão ter de fabricar 2 tipos de dies com geometrias espelhadas. Começam a ser demasiados integrados distintos.
 
Pois é, a AMD consegue com o mesmo die cobrir 3 gamas diferentes... Estes ai devem vir bem caros mesmo...

Agora 8 modulos HBM = até 512 GB de RAM por CPU... Em muitos casos de uso capaz de nem precisar de DDR5 e encher os slots de optane :msmiley1:
 
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E são NUMA forte e feio tanto com memória como IO separado por tiles. Há muitos casos onde epyc/threadripper vai ser preferível. São soluções tão diferentes que nalguns mercados nem sequer vão competir.
 
Ainda quero é perceber o grau de penalização de correr em modo UMA quando a alocação do processo está no banco de memória noutro "tile".
 
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