Processador Intel Sapphire Rapids (2022 - SR-SP e SR-X)

[Dark Kaeser]

Intel Xeon W-3400 Content Creation Preview​

For Intel, however, the idle power draw in particular increases significantly. On the previous generation Xeon X-3300 series, we are looking at about a 2x increase, going from 44W to 88W on the Xeon W-3375 38 Core. The difference is even larger on the new Xeons, with the w9-3495 going from 49W to 142W – nearly a 3x increase in idle power draw.

This is going to impact the system in two main ways: the cooler is going to have to work harder at idle (and thus be a small amount louder), and it will cost a bit more money to run your system. The raw costs aren’t that high in the context of the price of a system of this level (assuming it is idle 24/7/365, and energy cost is 15 cents per kWh, that is only a maximum difference of about $120 per year), but it is still a factor to consider.

With this information, we decided to present the results in this article using only the “High Performance” Windows power profile. We actually did all our testing with both profiles to see how much of an impact it made on each CPU, but since Intel Xeon benefits to much from using the “High Performance” profile, we are going to (for now) stick to presenting just those results.

https://www.pugetsystems.com/labs/articles/intel-xeon-w-3400-content-creation-preview/

no modo high performance 142w em idle

 

[Nemesis11]

56 Cores a 5.5 Ghz. Duas fontes Superflower de 1600 W, picos de 1900 W, -95 C.
Claro que isto é com Extreme OC.

 

[Dark Kaeser]

https://twitter.com/i/web/status/1647575279404191744

 

[muddymind]

https://www.cnbc.com/2023/04/27/intel-intc-earnings-report-q1-2023.html

Datacenters a cair 39%

Com os sucessivos atrasos de SPR que ainda nem sequer está a ser vendida a versão full featured e a continuarem a vender xeons icelake isto era mais do que previsível. Estão mesmo em maus lençóis.

 

[Nemesis11]

Intel's revenue for the first quarter dropped to $11.7 billion, which is $200 million higher than the company predicted back in January, but which is still down 36% year-over-year. The company lost $2.8 billion during the quarter as its gross margin declined to 38.4%. Despite posting the largest loss in its history, Intel paid $1.5 billion in dividends.

A Intel pode ter todas as razões para querer valorizar o seu stock price, mas com estes resultados e estando num mercado tão intensivo a nível de investimento, custa-me muito a perceber como é que dão dividendos de 1,5 mil milhões de $.

Eu não sei quais vão ser os resultados da nVidia e AMD e também não é muito justo comparar resultados de trimestres diferentes, mas só como indicação, nos últimos resultados, o revenue de Datacenter da nVidia, foi de 3,6 mil milhões de $ e da AMD, 1,7 mil milhões de $, sendo que são empresas mais pequenas que a Intel.
Datacenter, que costumava ser a "galinha dos ovos de ouro" da Intel, está em queda livre. Eles devem estar bastante preocupados.

 

[Dark Kaeser]

Para se ter uma ideia

https://twitter.com/i/web/status/1651696184166354944

Apesar do valor facturado, estão ainda assim a perder dinheiro.

 

[Nemesis11]

Um artigo semi-aberto, sobre o Emerald Rapids.

Intel Emerald Rapids Backtracks on Chiplets – Design, Performance & Cost​

At Intel’s recent DCAI Webinar, EVP Sandra Rivera revealed what Emerald Rapids, Intel’s 5th Generation Xeon Scalable Processors, would look like under the lid. Intel has decided to backtrack on chiplets for a generation by designing Emerald Rapids (EMR) using just 2 large dies. Its predecessor, Sapphire Rapids (SPR), had 4 smaller dies. Counterintuitively, Intel reduced the number of chiplets in their highest core count configuration from 4 to 2. This would make most scratch their heads, as everyone, including Intel, has been talking up chiplet disaggregation with smaller dies to improve yields and scale performance.

The largest variant EMR-XCC, bumps core counts to 64 from 60 on SPR. However, there are a total of 66 physical cores on the package, binned down to assist yields. Intel is not planning to productize a fully enabled 66-core EMR SKU like they did with 60-core SPR. EMR combines two 33-core dies, whereas SPR used four 15-core dies.

The other major change is that Intel dramatically increased shared L3 cache, from 1.875MB per core on SPR up to a whopping 5MB per core on EMR! That means a top-end SKU comes with 320MB of shared L3 cache across all cores, 2.84x the maximum that SPR offers. Local Snoop Filters and Remote Snoop Filters have also increased accordingly to accommodate the large L3 cache increase (LSF – 3.75MB/core, RSF – 1MB/core).

DDR5 Memory support has been increased to 5600 MT/s from 4800. UPI speeds for inter-socket communications have been upgraded from 16 GT/s to 20 GT/s. Oddly, despite higher inter-socket speeds, the number of total sockets supported is down from 8 to 2. This was likely done to speed time to market as it only affects a tiny portion of the market that AMD doesn’t compete in anyways. All this is drop-in compatible with existing “Eagle Stream” platforms on the same LGA 4677 Socket E1. Memory bus width and PCIe lane counts remain the same

Taking a closer look at the package, we notice that Intel was able to cram more cores and a whole lot more cache into an even smaller area than SPR! Including scribe lines, two 763.03 mm² dies make a total of 1,526.05 mm², whereas SPR used four 393.88 mm² dies, totaling 1,575.52 mm². EMR is 3.14% smaller but with 10% more printed cores and 2.84x the L3 cache. This impressive feat was achieved in part by reducing the number of chiplets, which we will explain shortly. However, there are other factors at play that help with EMR’s area reduction.

Although not discussed much publicly, Intel also did a complete ground-up re-design of Sapphire Rapids during its darkest days on its way to production E5 stepping. Believe it or not, there are two different physical designs and die sizes for the Sapphire Rapids chiplets.

All this talk about layout optimization and cramming more cores and cache in a smaller total silicon area would have you believe that EMR is cheaper to make than SPR. That is not the case.

Fundamentally, big rectangles just don’t fit neatly on a circular wafer. Going back to gross dies per wafer, we estimate that the EMR-XCC wafer layout matches SPR-MCC, meaning 68 dies per wafer. Assuming perfect yield and die salvageability, EMR could only do 34 CPUs per wafer, down from 37 CPUs per SPR wafer. It gets worse for EMR once factoring anything other than perfect yields, showing the disadvantage of going with larger dies.

Despite using less silicon area per CPU, EMR actually costs more than SPR to produce.

https://www.semianalysis.com/p/intel-emerald-rapids-backtracks-on

Parece-me que as maiores vantagens deste Emerald Rapids são o quase triplicar da Cache L3 por Core e a possibilidade de ter SKUs monolíticos até +/- 30 Cores.
O maior problema, especialmente para a Intel, é que mesmo com bons yelds, SKUs com uma ou duas dies com uma área de 763 mm², vão ter um custo de produção bastante alto.

 

[Dark Kaeser]

coisas estranhas, especialmente a parte da redução do número de tiles.

 

[JPgod]

Isso é capaz de dar uma dor de cabeça ao zen4? só 2 dies vai eliminar muitos problemas associados.

 

[Dark Kaeser]

Pois, possivelmente a decisão de diminuir os tiles ou dies, possam estar relacionados com a "comunicação interna" das soluções da "cola especial" que a Intel iria usar, é uma hipótese.

Agora é certo que os dies monolíticos têm vantagens associadas face ao uso de soluções MCM, mas é necessário ter em conta que várias empresas entre as foundries, EDA e OSAT, têm estado a trabalhar em múltiplas soluções de "die-to-die", em termos de melhoria da largura de banda, latência, etc.

Depois há as vantagens económicas em termos de custos de produção, essas são inegáveis para a AMD, e a verdade é que a Intel tem vindo a ter grandes dificuldades em acertar em determinados processos de fabrico, tornando esta decisão mais estanha ainda.

 

[Dark Kaeser]

https://twitter.com/i/web/status/1655728276357386241

Depois da preview no final de Fevereiro

Intel Xeon W-3400 Content Creation Review​

How Well Do the Intel Xeon W-3400 Processors Perform for Content Creation?​

Overall, the new Intel Xeon W-3400 series of processors are significantly faster than the previous generation, but this comes at the cost of much higher power consumption. And while the gen-over-gen performance is great in many cases, outside of a few isolated workloads, it is only enough to (at best) bring Intel on par with AMD’s Threadripper PRO 5000 WX-Series processors. In most cases, AMD maintains a small but measurable performance edge. This, combined with AMD’s lower power consumption, is going to make them a more attractive option than the new Xeon W-3400 processors in most content creation workflows.

https://www.pugetsystems.com/labs/articles/intel-xeon-w-3400-content-creation-review/#Introduction

 

[Dark Kaeser]

This is the 4-node Dual CPU Compute Blade HPE Cray EX420​

HPE says that this was for “Intel’s next-Gen Sapphire Rapids processor.” What is a bit strange about this placard is that the Sapphire Rapids processors are DDR5 RDIMM, not DDR4 processors.

Something that we did not catch earlier, but as we were looking at photos did not make sense, aside from the DDR4 and Sapphire Rapids spec, was the CPU cooler mounting.

When we looked at the photos of the HPE Cray EX420 (and validated with the service manual), the unit on display at SC23 was not an Intel Xeon Sapphire Rapids server. Instead, it was an AMD EPYC 7002 Rome system. We can see the telltale green carrier tab and AMD EPYC 7001-7002-7003 SP3 cooler mounting pattern.

Final Words​

The HPE Cray EX chassis has so much liquid cooling that it can be hard to tell what is underneath. Since we had the “Sapphire Rapids” launch months ago, this was not the case where it was an unreleased CPU. Instead, our best guess is that it is the blade HPE had on hand in Europe and so it put an Intel Xeon Sapphire Rapids placard on an AMD EPYC Rome system.

https://www.servethehome.com/this-is-the-4-node-dual-intel-xeon-blade-hpe-cray-ex420-amd/

É mais ou menos isto, mas não é bem assim

 

[Nemesis11]

Bug Forces Intel to Halt Some Xeon Sapphire Rapids Shipments​

Intel has confirmed that it has paused shipments of some of its fourth-gen Xeon Sapphire Rapids processors due to a newly-discovered bug, and it hasn't set a specific date for shipments to resume. We received a tip that Intel had paused the shipments, and following up on the matter, we learned several details about the issue from Dylan Patel, Chief Analyst at SemiAnalysis, who says shipments have been paused for certain SKUs since mid-June. We also followed up with Intel on the matter, and the company issued the following statement to Tom's Hardware:

"We became aware of an issue on a subset of 4th Generation Intel Xeon Medium Core Count Processors (SPR-MCC) that could interrupt system operation under certain conditions and are actively investigating. This issue was not observed when running commercially available software, and other 4th Generation Intel Xeon processor SKUs (i.e., XCC and HBM) have not exhibited the issue. Out of an abundance of caution, we did temporarily pause some SPR MCC shipments while we gained confidence in the expected firmware mitigation and expect to release remaining shipments shortly." — Intel Spokesperson to Tom's Hardware.

"Intel has faced another crop of design issues related to Sapphire Rapids MCC, the highest volume version of Sapphire Rapids. The 2-socket and 4-socket SKUs have paused shipments due to a timing issue since mid-June," Patel said.

Intel hasn't confirmed that the issue is confined to dual- and quad-socket SKUs, instead classifying this issue as limited to a 'subset' of the SKUs, and hasn't stated when the pause in shipments began. Intel also hasn't confirmed Patel's assertions that the bug is timing-related, or given us any clarification on the nature of the issue.

A timing issue could consist of any number of possibilities ranging from UPI interconnect to instruction timing issues, so the true nature of the bug remains nebulous for now. We do know that Intel can correct the issue with a firmware fix that apparently remains in validation for now, so the issue will not require a redesign or new revision/stepping to fix. Additionally, since new firmware is an adequate fix, Intel might not be required to replace any processors already in the field — although it could pose a validation headache for its customers.

https://www.tomshardware.com/news/bug-forces-intel-to-halt-sapphire-rapids-shipments

A Intel tem que ir à Bruxa. Ainda por cima, os MCC são os SKU mais competitivos do Sapphire Rapids.

 

[Dark Kaeser]

Intel Xeon MAX 9480 Deep-Dive 64GB HBM2e Onboard Like a GPU or AI Accelerator​

The Intel Xeon MAX 9480 combines 56 cores with memory on the package. The memory is not standard DDR5. Instead, it is 64GB of HBM2e, the same kind of memory found on many GPUs and AI accelerators today.

While we do not have these CPUs, what we do have is a development platform so let us take a look at that quickly before moving on.

The CPU is not the only Intel “MAX” product found in the system, as there was an Altera FPGA, the MAX 10 onboard as well.

At this point, we have set up one of the key challenges of Xeon Max. Just how many options there are. To be clear, you can put the CPUs into a system, without DDR5, and the system boots up normally. Likewise, you can then add DDR5 and it will work normally, but the Xeon Max has extra options for tuning.

We left Hyper-Threading on, ran a few different workloads, and found some really interesting results. For several of them, we are just going to say we are directionally similar to what Intel saw, but Intel is doing more tuning so we would use Intel’s numbers.

Of course, the elephant in the room is AMD EPYC. There are many workloads where having chips like the AMD EPYC 9684X with huge caches and 96 cores is very good. There are others where having HBM2e helps keep cores fed.

https://www.servethehome.com/intel-...b-hbm2e-onboard-like-a-gpu-or-ai-accelerator/

 

[Dark Kaeser]

Pelos vistos vai haver um "refresh" dos Sapphire Lake HEDT

https://twitter.com/i/web/status/1754116735865880949

https://twitter.com/i/web/status/1754118908108509404

 

[Dark Kaeser]

Argonne Aurora Walk About Video​

The video follows computer scientist Victor Mateevitsi and computational scientist Christine Simpson as they walk about the new Argonne Leadership Computing Facility.

Aurora takes up 10,000 sq ft (292 sq m) of floor space or, as the video indicates, using NBA Basketball court units of measure that would be a value of 2. There are 300 miles (483 km) of optical cabling in the 600-ton (544311 kg) machine that is arranged in an array of 8×20 8ft tall (2.5 m) racks, each with 64 compute blades.

There is also a good description of the blade hardware detail and the internal water cooling needed to achieve this density. The money shot, however, is the mechanical room with massive water cooling infrastructure. Not your water-cooled Gammer case.

https://www.hpcwire.com/2024/02/27/argonne-aurora-walk-about-video/