Processador Intel Sapphire Rapids (2022 - SR-SP e SR-X)

É a mesma hierarquia a nível de memória que existia no Xeon Phi "Knights Landing", tirando o "Hybrid Mode", que não parece existir neste "Sapphire Rapids".
A4rgQOD.png


O melhor modo irá depender de cada aplicação, com a diferença que agora deverá haver penalizações na comunicação entre Tiles e é usado HBM em vez de HMC.

https://www.alcf.anl.gov/files/Hammond_ALCF_Theta_HBM_overview_PUBLIC.pdf
https://www.alcf.anl.gov/files/HC27.25.710-Knights-Landing-Sodani-Intel.pdf
https://sites.utexas.edu/jdm4372/20...ntel-xeon-phi-x200-knights-landing-processor/
https://www.intel.com/content/dam/d...ocuments/intel-xeon-phi-memory-management.pdf

Já agora, aquele artigo da Cnet de visita a uma fábrica da Intel, parece ter lá uma foto da versão com HBM.
znkWJ8q.png
 
Os coolers (dual CPU) sao as 2 pecas metalicas na frente, com adesivos pretos e amarelos e um "caixa" azul com o cooling das memorias entre eles.
 
iu


Delidding an unreleased 56 Core Intel CPU - Sapphire Rapids Xeon​





Atos’ energy-efficient supercomputer expands HPC system at Technische Universität Dresden​


This new HPC installation includes more than 600 nodes of Intel's upcoming CPU generation "Sapphire Rapids" with large main memory and high memory bandwidth. TU Dresden will thus be able to perform high-quality data analyses and simulations in a timely and flexible manner.
Clicar para expandir...
https://atos.net/en/2022/press-rele...-hpc-system-at-technische-universitat-dresden
 
Bons Scores. Já agora, Cinebenchs, parece que sem AVX512 e AMX ligado:
IEHEeL1.jpg


CPU-Z entre este CPU, o 8380 e o 7773x:
QqAwYLs.jpg


Já agora:
SapphireRapids with the HBM2e version will have a set of embedded OS features that can be unlocked for a fee, perhaps loading the system into HBM2e memory.
(The HBM2e on the processor has multiple control modes)
Clicar para expandir...
Interessante. Parece que há modos na versão HBM2e, que só podem ser desbloqueadas, pagando à parte. A Intel já tinha anunciado que iria ter opções no Processador que seriam pagas à parte (Subscrição?).

XSZ33DD.jpg


Aquele "CPU Power Limits (Max)" de 624W por 32 segundos, é um valor de um dos Turbos ou um Limite de Segurança?
Pressuponho que seja um limite de segurança, dado o valor ser tão alto e por tanto tempo.
 
O mesmo não conseguiu efectuar testes de AV-512, mas...

https://twitter.com/i/web/status/1492532868202909698

EDIT: se calhar o gajo até tem razão, estava agora a ver o Phoronix

Intel Software Defined Silicon Planned For Integration In Linux 5.18
We still don't know what features Intel is planning to capitalize upon with their Software Defined Silicon "SDSi" functionality in future CPUs, but it turns out the kernel mainlining of the necessary software support is now expanded to land with Linux 5.18. With the SDSi kernel support coming together rather quickly, it's possible we could be seeing Software Defined Silicon rather soon.
Clicar para expandir...
Based on this rather rapid timing since seeing the patches quickly revised through Q4 and now aligning for Linux 5.18, it's possible SDSi may make its debut for Xeon Scalable "Sapphire Rapids" or perhaps more likely the successor to the Rocket Lake Xeon W-1300 / E-2300 series, a.k.a. the Alder Lake Xeon chips... There have been various rumors recently regarding Alder Lake Xeon chips and would make more sense if Intel is going to make use of SDSi there with their entry-level server/workstation chips rather than with high-end Xeon Scalable processors. In any case with there some interest/emphasis on having SDSi ready for Linux 5.18, it's presumably to prepare for chips coming this year and not 2023~2024.
Clicar para expandir...
One possibility that comes to mind is Intel gating AVX-512 with Alder Lake Xeon chips as an SDSi upgrade feature. We know Alder Lake's P cores have AVX-512 when the E cores are disabled and enabling AVX-512 from the BIOS, but more recently motherboard vendors have begun outright removing that functionality from their Alder Lake S consumer desktop motherboards.
Clicar para expandir...
Anyways, long story short, Intel Software Defined Silicon is expected to land with Linux 5.18. Intel has not offered any public announcements or guidance yet how they plan to commercialize around SDSi but will be interesting to see... While just speculation for now, given the current state with Alder Lake on the consumer side with AVX-512 in fact being present for P cores, I can't help but wonder if their upcoming entry-level Xeon chips could have AVX-512 for P cores as an opt-in/upgrade feature. We'll see.
Clicar para expandir...
https://www.phoronix.com/scan.php?page=news_item&px=Intel-SDSi-Linux-5.18
 
Última edição:
A Intel já tinha anunciado o SDSi há uns tempos. Não estava à espera que colocassem AVX-512 atrás dessa paywall.
Seria uma boa noticia para quem não precisa de AVX-512 se os processadores sem AVX-512 fossem mais baratos, mas duvido que irá ser isso que vai acontecer.....
Seria mais compreensível se colocassem o AMX ou diferentes modos de funcionamente da HBM2e.

Espero que não se confirme o AVX-512 ficar por trás do SDSi.
 

ISSC 2022: How four dies become a 'monolithic' Sapphire Rapids​


Four times 400 mm² (the actual size is slightly less than 400 mm²) sit on the package and could not be manufactured as a 1,600 mm² chip. According to Intel, each of these chips has between 11 and 12 billion transistors.
Clicar para expandir...
First, however, the speakers lost a few words about the production of the chips themselves. These are manufactured in Intel 7 (10 nm) with dual-poly-pitch SuperFin (SF) transistors, a more than 25% higher MIM density (metal insulator -Metal) compared to SuperMIM and a metal stack with an optimized routing layer with 400 nm spacing. The latter measure is essential, since the latencies for the interconnect should be reduced.
Clicar para expandir...
isscc-2022-intel-sapphire-rapids-1_1920px.png

At the ISSCC 2022, Intel disclosed the internal layout for the first time. Each chip is connected to each other via two or three interconnects called Multi-Die Fabric IO (MDFIO). So we see a certain asymmetry here, the effects of which we do not yet know. In addition to the bandwidth, the efficiency of such a connection is decisive, because it doesn't help much if the interconnect absorbs a large part of the energy and therefore less is left for the actual cores and other components.
Clicar para expandir...

Lots of redundancy to improve yield​

But even if the chips used for Sapphire Rapids are comparatively small at 400 mm², Intel has decided to take many measures to compensate for any defects based on previous experience with production in 10 nm. These go beyond what Intel has previously used in terms of repair and recovery methods and affect the core areas (the actual performance cores) as well as the caches, uncore and I/O blocks.

Redundant circuits in hazardous areas are a measure to compensate for a possible defect.
Clicar para expandir...
Overall, according to Intel, 74% of the chip is recoverable. However, once a processor has been assembled from four chips, its individual functions and connections can no longer be tested that easily. Intel also had to come up with ways and means to be able to carry out tests directly on the EMIB connection, for example, or provides GPIO pins and also provides for the use of JTAG.
Clicar para expandir...
isscc-2022-intel-sapphire-rapids-2_1920px.png


https://www-hardwareluxx-de.transla...sl=de&_x_tr_tl=en&_x_tr_hl=pt-PT&_x_tr_pto=sc
 
Estava à espera de melhores resultados em Single Core.
Em Multi Core e comparando apenas com o Ice Lake, por ser o único a usar só 1 Socket, também tem uns resultados bastante desanimadores.
Pode ser que desse ES2 à versão final, as coisas melhorem um pouco. Em situações onde seja importante Bandwidth, também deve fazer melhor figura.
 

Nvidia taps Intel’s Sapphire Rapids CPU for Hopper-powered DGX H100​


Jensen Huang, co-founder and CEO of Nvidia, confirmed the CPU choice during a fireside chat Tuesday at the BofA Securities 2022 Global Technology Conference. Nvidia positions the DGX family as the premier vehicle for its datacenter GPUs, pre-loading the machines with its software and optimizing them to provide the fastest AI performance as individual systems or in large supercomputer clusters.

Huang's confirmation answers a question we and other observers have had about which next-generation x86 server CPU the new DGX system would use since it was announced in March.
Clicar para expandir...
"We buy a lot of x86s. We have great partnerships with Intel and AMD. For the Hopper generation, I've selected Sapphire Rapids to be the CPU for Nvidia Hopper, and Sapphire Rapids has excellent single-threaded performance. And we're qualifying it for hyperscalers all over the world. We're qualifying it for datacenters all over the world. We're qualifying it for our own server, our own DGX. We're qualifying it for our own supercomputers," he said at the Tuesday event.
Clicar para expandir...
https://www.theregister.com/2022/06/07/nvidia_intel_sapphire_rapids/


EDIT: aparentemente mais um atrasosinho confirmado pela Sandra RIvera - Executive Vice President, General Manager, Datacenter and AI Group at Intel
At this point we are building in more platform and product validation time, so we see Sapphire, you know the ramp being later in the year than what we had originally forecasted, but the demand is still very high.
Clicar para expandir...
So the process is healthy, the capacity picture is good, but you know we’ve got some of these other issues that we’re dealing with and customers on that match that issue still working through that.
Clicar para expandir...
https://www.computerbase.de/2022-06/intel-xeon-sapphire-rapids-steht-im-stau-teil-2/

As afirmações são de uma conferência

BofA Securities Global Technology Conference​

https://www.intc.com/news-events/ir.../bofa-securities-global-technology-conference
 
Última edição:
Inicie sessão ou registe-se para poder participar.
Back
Topo