blaster_00
Power Member
“reimagined” way of designing chips.
Não sendo quantum computing, cheira-me ao que a AMD tem andado a projectar há anos: Fusion/HSA, com a memória integrada e partilhada ondie no próprio C/GPU.
“reimagined” way of designing chips.
Não sendo quantum computing, cheira-me ao que a AMD tem andado a projectar há anos: Fusion/HSA, com a memória integrada e partilhada ondie no próprio C/GPU.
Xeon Phi is dead, long live the Xeon-H
Behind closed doors, Intel revealed a few key facts at the SC17 conference.These did not remain secret in the Denver Convention Center for long.
Intel will replace the Xeon Phi from 2019/20 with the special Xeon ISX-H.
2019/20 will then follow the Ice Lake Scalable Xeons (ISX-SP) in 10 nm +, with up to 38 cores, eight memory channels and up to 32 GB of High Bandwidth Memory (HBM2) on board.But one hears from a moderate bandwidth of 650 GB / s - for comparison: NEC Aurora creates with HBM2 1.2 TB / s.The normal Xeon SP line will then be extended by a special version ISX-H (codename Knights Cove) with 38 or 44 cores, which is intended as a successor to the Xeon Phi.
The 44-Kerner should be an MCM consisting of two chips of 22 cores. He should be about 40 percent faster in the Linpack than the normal ISX with 24 cores and should therefore run at around 30 percent lower clock. You could already hear about the successors Ice Age and Knights Run planned for 2021, which are probably intended for Aurora.
The AVX512 extension VNNI (Vector Neural Network Instructions) is then offered by the ISX-H.
The main reason for leaving the Xeon Phi should be the cost.Unlike Nvidia at Tesla, Intel can not exploit synergies with graphics chips in the Xeon Phi and can not afford any large numbers.At Nvidia, millions of gamers are making sure that the GPU design pays off.
In addition, there are apparently problems with the 10-nm process at Intel, so that the yield is low for large chips, which further increases the costs.
Also the dissatisfaction of the phi-users could have played a role.The implementation of AVX512 is only partially compatible with the Xeon and the code is not binary compatible because of other prefixes.
In addition, the Xeon Phi Knights Landing (KNL) requires elaborate optimization, because otherwise, according to the experience report of NERSC with the KNL supercomputer Cori reached on average only 70 percent of a Haswell node.Optimized for both, he can overtake the Haswell, but also just by 10 percent.
It was just last month Intel began publishing more GCC patches that will be supported by their Icelake processors, the successor to the yet-to-be-released Cannonlake CPUs. The GNU Compiler Collection has initial Icelake support for GCC 8.
On the LLVM side, it's a similar story. Intel recently published the Icelake target patch for LLVM/Clang. That's going into LLVM Clang 6.0 that will be released as stable in 2018.
Coming out today in LLVM SVN/Git is initial support for VNNI. The Intel Vector Neural Network Instructions instructions are their addition of deep learning instructions being added to their Icelake processors. It's being treated as part of AVX-512 and initially is the vpdpbusd and vpdpwssd instructions
According to Barry Davis, GM of the enterprise and HPC group at Intel, the reality is that this architecture needs to be production ready by 2021, which is not much time, especially if is software footwork required from users. That pares the options down, but also begs several questions about the approach. From what we could gather, a pure CPU is the target—nothing that requires fancy offload models or novel approaches to programming or thinking about problems.
The architecture we are moving toward for exascale is not something we just dreamed up in the last six months or even year. We’ve been on working on this for a long time. What the two-year pull-in of the timeline to 2021 does is accelerates our roadmap. We could shift quickly to meet that because we’ve been working on this for a while. A two-year pull-in was not easy and we were already trying to accelerate the roadmap before this and consider how to bring in some of the future Xeon implementations and bring those closer into the market. We are not doing something just for exascale; it was something we planned to do, so this is a lot easier to do than it may seem.
Everything is hitting within a window where we had already targeted that process node in that timeframe. It’s not like we had to say, and this is just an example not a statement about the chip, that to make this work we had to move this from 14nm to 10nm. This was our timeframe for this processor anyway.
ince we are on a CPU path here, this is not going to be a strategy that completely disrupts the ecosystem. We want to run this up the middle with existing models (OpenMP as an example) but there is enablement that needs to happen.
You’re talking about hardware architectures but I like to think of things in terms of workloads. So there are, like you say, FPGAs, GPUs, vector machines and things like the PEZY chips in Japan (as one example). Many of those are offload for particular codes that have to be sent over a bus for execution. That’s fine but we are a CPU company. We like to think about codes executing on our platform without the latency and offload. There are areas where that works well, but it doesn’t work for everything and CPUs do.
There are a lot of processor options; some with volume, some without. There are PEZY machines and there’s volume there and GPUs and there’s definitely volume there. Truly novel architectures mean you have to change how you think about things. As long as tools and applications and development activity is similar to what we know, it is not novel. I can’t say if what we are doing is novel, I’ll let you draw your own conclusions, but to me, novel means big changes for end users and as we discussed, we are not trying to be disruptive to the ecosystem.
http://www.newsweek.com/quantum-com...ra-powerful-machines-closer-725955?yptr=yahooa key component in quantum computers—known as a microwave circulator—can be miniaturized by a factor of 1,000.
Intel's Gen. 12-based discrete GPU is code-named "Arctic Sound." Will connect to Intel processors via EMIB.
Intel's Gen. 13-based discrete GPU is code-named "Jupiter Sound."
Intel is making progress in its development of a new discrete GPU architecture, after its failed attempt with "Larrabee" that ended up as an HPC accelerator; and ancient attempts such as the i740. This comes in the wake of the company's high-profile hiring of Raja Koduri, AMD's former Radeon Technologies Group (RTG) head. The company unveiled slides pointing to the direction in which its GPU development is headed, at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco. That direction is essentially scaling up its existing iGPU architecture, and bolstering it with mechanisms to sustain high clock speeds better.
The company's first 14 nm dGPU prototype, shown as a test-chip at the ISSCC, is a 2-chip solution. The first chip contains two key components, the GPU itself, and a system agent; and the second chip is an FPGA that interfaces with the system bus. The GPU component, as it stands now, is based on Intel's Gen 9 architecture, and features a three execution unit (EU) clusters. Don't derive numbers from this yet, as Intel is only trying to demonstrate a proof of concept. The three clusters are wired to a sophisticated power/clock management mechanism that efficiently manages power and clock-speed of each individual EU. There's also a double-clock mechanism that doubles clock speeds (of the boost state) beyond what today's Gen 9 EUs can handle on Intel iGPUs. Once a suitable level of energy efficiency is achieved, Intel will use newer generations of EUs, and scale up EU counts taking advantage of newer fab processes, to develop bigger discrete GPUs.
Mas calma lá, a EMIB não obriga a que estejam no mesmo "chip"? Eu fui ver isso da EMIB, e pareceu-me assim por alto ser apenas outra forma de ligar componentes dentro da mesma placa, e se não for usado como uma placa gráfica, teria que estar integrado com o CPU, ou pelo menos com o substrato onde está o CPU, de alguma forma.
Intel Unveils Discrete GPU Prototype Development
Bonus: Apparently @Rajaontheedge is redefining Arctic Sound (first Intel dGPU), was originally targeted for video streaming apps in data center, but now being split into two: the video streaming stuff and gaming. Apparently wants to “enter the market with a bang.”
Eassa confirmed this with multiple sources, and I spoke independently with a source of my own to back up this statement. I'm confident this is more than rumor and speculation.
isso significa que vão fazer GPU's ? seria muito bom ! ou percebi mal ? mesmo a longo prazo não é boa noticia?
só uma questão de leigo, imaginemos que eu quero fazer um GPU , não tenho que pagar uma batolada de licenças e coisas dessas ?
A Intel já faz GPUs há muito tempo
Seria interessante se a Intel entrasse no mercado
Intel could unveil its new graphics card at CES 2019
Intel has been working hard on their new GPU with industry sources telling TweakTown that they've reached the end of this first step, and are now preparing for the big launch.
My sources are telling me to expect something late this year with all attention to be placed on Intel at CES 2019 in January, where Intel could unveil their new GPU. A discrete graphics card launch from Intel would be a huge deal to gamers, as NVIDIA has no competition in the high-end graphics card market from AMD whatsoever.
Pelo menos a intel deve ter capacidade de fabrico dos chips e VRAM para encostar a AMD e a NVIDIA nesta loucura de preços só para "mineiros"