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Intel is following in AMD's footsteps
Monday 16 October 2006, 15:37
SO, WHY IS IT that a company - Intel in this case - with a market cap of ~$115,000,000,000 (give or take ten billion), that has succeeded by whatever means it could get away with, has trouble matching wits with a much smaller rival - AMD in this case - with a market cap of ~$12,000,000,000 and which has had to struggle just to survive?
Some (very) brief history ... for context
Almost since their founding just one year apart (Intel in 1968 and AMD in 1969), these two arch-rivals have seemed to be in a constant state of war: Intel for dominance and AMD for survival (and respect).
In 1982, IBM forced Intel to sign a contract to license AMD as a second-source manufacturer of 8086 and 8088 processors. (IBM's policy then required at least two sources for its chips.) In 1986, Intel abrogated that agreement and consequently, in 1987, AMD sued. Eventually, in 1994, the California Supreme Court decided in AMD's favour and, in 1995, Intel signed an agreement allowing AMD to use 286, 386, and 486 microcode. In addition, though the agreement details are still largely secret, AMD and Intel appeared to have reached an understanding to share, without licence fees, any enhancements to the core x86 architecture - hence Intel's cloning of AMD64 without legal consequences or, for that matter, AMD's use of the SSEn instruction sets.
Most recently, in 2005, Advanced Micro Devices (AMD) announced that it had filed an antitrust complaint against Intel after concluding that what it called Intel's tactics of bullying and bribing its customers could no longer be tolerated. In Japan, where the Fair Trade Commission had notified Intel in 2005 it had been found guilty of "unfair business practices", AMD had seen its share of the Japanese PC market between 2002 and 2004 halved to 10.4 per cent. Similar antitrust investigations are current underway in both the EU and South Korea.
Current events (1999 till now) ...
Now lets take a look at where lil' ol' AMD has lately managed to out-engineer its much larger rival and where Intel has been forced to follow (copy):
First - AMD64 (a.k.a. X86-64). When AMD first announced its intention to extend the venerable x86 architecture, Intel derided the idea and refused to even acknowledge that it had a parallel effort afoot – just in case. It feared, and as it turned out, reasonably so, that a viable x86-64 would detract from its most favoured child – Itanium. What was even worse is that at the same time AMD had forced Intel into a performance race: Athlon v. Pentium. This was the last thing Intel wanted or needed. The result being Intel no longer had the performance gap it needed between IA32 and IA64 to drive the adoption of the Itanium. Intel relented and copied AMD64.
Second – a multi-core architecture, which AMD had designed into Athlon/Opteron from the beginning with a memory controller intended to support the multiple cores. Only when AMD had reached a mature 90nm processing technology was it able to reliably implement dual-core parts. Intel, of course, couldn't allow this to go unchallenged and introduced a "dual-core" Pentium that was in reality simply two dies packaged together. Of course, this design had limitations: core-to-core communication had to go off chip, via the FSB. And, as is usual with Intel, this required yet another new chipset (i.e., motherboard). In contrast, the dual-core Athlon/Opteron architecture uses a crossbar switch for core-to-core communications (never leaving the chip) and required only an BIOS upgrade – it pays to think ahead.
Third - an integrated memory controller (IMC), which of course Intel criticised as "not as good as" its FSB architecture. As recently as June 2006 an Intel presentation contained such critiques of an IMC as: "Tied to specific memory technology", "Requires more pins per CPU", and "Increases CPU die size and power". Well somehow Intel overcame these objections and once again decided to follow in AMD's footsteps and add an integrated memory controller into its CPU roadmap. The interesting question is, will Intel follow AMD and adopt NUMA (vs. SMP) in its upcoming architecture?
Fourth – a high-bandwidth, low-latency, chip-to-chip interconnect – HyperTransport. When it first appeared in 2001, Intel was coincidentally introducing 3GIO (a.k.a., PCI-Express [PCI-e]) and, not surprisingly, dismissed HyperTransport as unnecessary and proprietary. PCI-Express, primarily a board-to-board (backplane) interconnect, would prove HyperTransport redundant. Yet again, Intel relented and announced the "Common System Interface" (CSI) as part of its Nehalem micro architecture. And you guessed it, Intel's CEO and perpetual pitchman Paul Otellini assures us it will be better than the original - HyperTransport: faster, lower latency, "It slices! It dices! It makes julienned fries - whatever those are!" etc., etc.
And, finally, fifth - AMD's Torrenza Initiative and Intel's "pump fake" – Geneseo. In 2004, the HyperTransport Consortium announced HTX, a HyperTransport I/O expansion slot for high-performance systems. These slots used the same mechanical connector as an x16 PCI-e slot but only offers a fraction of HyperTransport's full bandwidth: 41.6 GB/s v. 6.4 GB/s. (PathScale's InfiniPath HyperMessaging HTX adapter offers a low latency cluster interconnect for MPI applications.) Expanding on this concept, in June AMD released its Torrenza Innovation Socket, a plan to open up its Opteron socket specification, allowing third party developers to offer co-processors. As part of this, AMD released a detailed description of a two-socket motherboard with an Opteron in one socket and a co-processor in the other. With the high-bandwidth, low-latency, and cache coherency offered by HyperTransport - the era of co-processing has effectively returned.
Not to be outdone, Intel cobbled together a quick response - Geneseo - based on PCI-e adaptors. But if you are, 1) designing a co-processor that works closely with the CPU and hence requires cache coherency, or, 2) targeting applications which require minimum latency (e.g., MPI adaptors), then Geneseo ain't it. A more general question to ask is, who would develop a co-processor - "accelerator" - which fails to offer the maximum acceleration? Geneseo is best seen as an effort by Intel to freeze the competition's momentum, giving it time to complete development of CSI and then offer a CSI-based Torrenza.
With the acquisition of ATI, AMD now as the potential to offer its own GPUs to fill those co-processor sockets, ushering in a more practical, commonplace use of CP-GPU based application development. Eventually, the GPUs could be offered as addition cores on the Opteron/Athlon die.
Not surprisingly, Intel has of late been trying to bolster its own in-house digital-graphics talent. And there are the reports (rumours) Intel is interested in acquiring Nvidia. Yet again reacting to AMD.
"It's a bad idea until we copy it, then it's a great idea!"
Given these trends and the Andy Grove, Machiavellian mentality which permeates Intel - who cares who invented it, only who's selling it. After all, copying others is ultimately practical and, maybe for Intel, ultimately a successful strategy.
Postscript
Lest I appear to be too one sided in this article, it should be noted that Intel with its introduction of the Core 2 has regained the lead from AMD at the micro architecture level. Although, AMD appears to have more than enough headroom in the current K8 micro architecture for it to make up the difference.
The upcoming "Barcelona" (K8L) should match Intel's latest-and-greatest but only time will tell. Another problem that has consistently dogged AMD is its apparently permanent position of lagging one generation behind Intel in its manufacturing process, though SOI does offer its own unique advantages – read that Z-RAM. µ
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