Memory Overclock Timings

Boas... Existe muitos Tópicos e vídeos como fazer um overclock a um CPU hoje em dia é relativamente fácil adquirir esse conhecimento.
Venho desafiar a malta a meter um tutorial de como pegar numa RAM com o XMP ligado a 3800 ou 4000 MHz c16 ou c17 e trabalhar os Timings e os subtimings dela para baixar a latencia o mais possível.
Ex: Todos os TC, TRC, TW, TRF etc etc.
Cumprimentos

P. S: Se existir já um tópico sobre isto peço desculpa mas não encontrei.
 

Websync

Power Member
Não há nenhum segredo.
Baixas umas timmings e vês se tens boot, se tiveres, tens que testar a estabilidade da memória com programas como memtest86. Rinse e repeat para cada timming ou subtimming.
É um processo demorado e trabalhoso, dai xmp ser o mais aconselhável para a grande parte das pessoas.
Tens que ter um entendimento básico do que cada função faz, por exemplo tRDRDSC/tWRWRSC/tRDRDSCL/tWRWRSCL são particularmente importantes em ryzen.
Se tens ryzen aconselho-te a fazeres download do dram ryzen calculator, da-te uma base para começares que é bem melhor que começar do 0.
 
Os Timings principais são fáceis de baixar os sub Timings são mais difíceis...
A cada mexida que fazes provavelmente terás que mexer na voltagem também.
Alguém conhece algum tutorial porreiro.
P. S: Meu CPU é Intel
 

Websync

Power Member
O que te estava a tentar dizer é que fazer OC a memoria nao é um processo em que possas seguir nenhum tutorial, e claro, vais ter que mudar a voltagem da tua ram, mas tens que ter cuidado, por exemplo c die nao gosta mais que 1.35v, já b-die leva com 1.5 a brincar...

Tens aqui leitura para mangas:

tCL: Column Access Strobe (CAS) Latency, the delay in clock cycles between when the IMC activates a column of memory for reading and when the address in the column is actually read. Essentially, this is how fast the sense amplifiers work. This is supposedly the most important timing because the CAS, i.e. the strobe capacitor, activates last (kinda), and so only when that happens can data be read. Thus lower tCL means less cycles between when the CPU asks for data and the data is actually read.





tRCDWR: Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write). The delay between when a row address is activated and when a column address is activated for writing. This is how fast data from the RAM transfers to the sense amplifiers. The reason for why this timing is important is pretty similar to tCL: it’s the amount of cycles between when a row is activated and when a column is activated, so lower tRCDWR means less delay before writes.




tRCDRD: RAS to CAS Delay (Read). The delay between when a row address is activated and when a column address is activated for reading. Basically tRCDWR but for read operations.

tRP: Row Precharge Time. The amount of time it takes to deactivate (precharge) one row of memory and activate a new row of memory (on the same rank). This is how fast data is transferred from sense amplifiers back to the cells. You can think of this as essentially the “cooldown” between memory operations on the same rank, or side, of a DIMM. (Sidenote: it’s not necessary true that rank = side, especially for 4 or more DIMMs. If you’re interested, here’s buildzoid’s video about memory ranks


tRAS: RAS Active Time. The minimum time between a row of memory being activated and precharged. This is the amount of cycles that a row of memory can be accessed for reading/writing. Just like the name suggests, it’s how long the RAS capacitor stays active once it receives a signal from the IMC.

CR: Command Rate. The amount of consecutive clock cycles that commands must be sent to the DRAM to ensure that the command is executed. If this is 1T, the IMC sends each command the memory once; if it’s 2T, then the IMC sends each command twice in a row. Thus, it should be pretty intuitive that a command rate of 2T can help OC stability: if there is any kind of issue with the memory not receiving/executing the command sent in the first signal, it has a second chance.

tRC: Row Cycle Time. The minimum amount of time between activation commands to the same memory bank. Just like the name suggests, this is the amount of cycles that the IMC has to wait before it can send another activation signal to a bank of memory.

tRCPage: Page Time Line Period. EDIT: As mentioned in this patent, is the number of activate commands that can be sent to a row within a predetermined window of time.

tRRDS: RAS to RAS Delay, Different Bank Group. The delay between two row activations across different bank groups. Once a row is activated in one bank group, the IMC has to wait this many cycles before a row can be activated in another bank group.


tRRDL: RAS to RAS Delay, Same Bank Group. The delay between two row activations within one bank group. As you probably can guess, this is the same as tRRDS, but regarding a single bank group instead of multiple bank groups.

tFAW: Four Activate Window. The amount of time in which four row activations can occur within the same rank. Pretty self explanatory, if the IMC needs to access four different rows of memory within one rank of a DIMM, it will take tFAW cycles to do so.

tFAWDLR: All I know is that it’s related to tFAW.

tFAWSLR: See tFAWDLR.

tWTRS: Write to Read Delay, Different Bank Group. The delay between a successful write command and a read command across different bank groups. Once a write command has been finished on a memory address, this is the amount of cycles before a read command can be executed on a row in a different bank group.

tWTRL: Write to Read Delay, Same Bank Group. The delay between a successful write command and a read command within one bank group. Just like with tRRDS and tRRDL, the only difference between this and tWTRS is which bank groups are involved.

tWR: Write Recovery Time. The delay between a successful write command and the active bank being precharged. Once a write command to a memory address has finished, it takes this many cycles before the bank (not just the row) containing that address is deactivated.

tRDRD _ _ (_): Read to Read Delay. The delay between two read commands. Self explanatory, the number of cycles that must pass after the IMC sends a read command before it can send another. There are 4 variants of this:

tRDRDSC: tRDRD, Different Bank Group. Involves two rows in different bank groups.

tRDRDSCL: tRDRD, Same Bank Group. Involves two rows within one bank group. This one is notable as it has a large impact on bandwidth.

tRDRDSD: tRDRD, Different Rank. Involves two rows in different ranks of a DIMM.

tRDRDDD: tRDRD, Different DIMM. Involves two rows on different DIMMs.

tWRWR _ _ (_): Write to Write Delay. The delay between two write commands. Think tRDRD but with two write commands instead of two reads. Again, there are 4 variants:

tWRWRSC: tWRWR, Different Bank Group. Involves two rows in different bank groups.

tWRWRSCL: tWRWR, Same Bank Group. Involves two rows within one bank group. This one is notable as it has a large impact on bandwidth, like tRDRDSCL.

tWRWRSD: tWRWR, Different Rank. Involves two rows in different ranks of a DIMM.

tWRWRDD: tWRWR, Different DIMM. Involves two rows on different DIMMs.

tRFC: Refresh Cycle Time. The amount of time between a refresh command and an activation command being executed by the DRAM. Refresh commands are what make DRAM special, and are when a section of memory is read and then the data there immediately rewritten to the same addresses. Refreshing a section of memory prevents it from being physically lost by way of leakage. Anyway, this is the amount of cycles after a refresh command has been issued before a row of (that section of?) the memory can be read again.

tCWL: CAS Write Latency. The delay between when the IMC activates a column of memory and when a write command is executed. Although not in the timing abbreviation, tCL specifically controls read operations; this timing, then, is just tCL but for write operations. (I’m not sure why it’s not as important as tCL...) According to AMD, this timing greatly impacts stability, which again makes sense, as it is related to the famous tCL.

tRTP: Read to Precharge Delay. The delay between a read command and a row precharge in the same rank. This is the minimum amount of cycles between a row of memory being read and a different row in the same memory rank being deactivated.

tRDWR: Read Write Command Spacing. The amount of turn-around clocks between a read command and a write command on the same rank. I’m not entirely sure what a turn-around clock is, but I believe it refers to tRDRD/WRWR timings. Anyway, this is the amount of those cycles that must pass after a read command is sent to a memory address before the IMC can send a write command to a different address on the same rank of a DIMM. According to AMD this timing has a large effect on throughput.

tWRRD: Write Read Command Spacing. The amount of turn-around clocks between a write command and a read command on the same rank. This is basically tRDWR, but after a write command and before a read command instead of vice versa. According to AMD this timing has a large effect on throughput.

tCKE: Clock Enable Time. The minimum amount of time it takes for a CKE pulse to occur. This one is one of the more technically involved timings here, so I may not have this exactly correct. From what I can tell, a CKE pulse changes a DIMM’s power state. There are two kinds: CKE LOW and CKE HIGH. CKE LOW causes the DIMM to enter powerdown mode for the duration of a clock cycle, while CKE HIGH causes the DIMM to exit powerdown mode for the rest of a cycle. CKE LOW prevents the memory from receiving unwanted commands (i.e. puts it in an idle state), whereas CKE HIGH allows the memory to receive all commands from the IMC (i.e. puts it in an active state).

tRPPB: Row Precharge Time, Per-Bank/Single Bank. I believe this is the minimum amount of time between a row of memory being precharged and another row in the same bank being available for reading. It may be the number of extra cycles in addition to tRP that must pass between two row precharges, though I’m not sure, since the sources I found only discuss this in regard to LPDRAM. For LPDRAM, the data sheets I found say tRC = tRAS + tRPPB. However I don’t know that that applies to SDRAM.

tRCPB: Row Cycle Time, Per-Bank/Single Bank. I couldn’t find anything whatsoever on Google, so this name is only an inference based on my findings for tRPPB. I presume this is also something related to LPDRAM specifically.

tRRDDLR: I have no idea.

tRDRDBAN: Read to Read Timing Ban. Once a CAS has been activated for a read operation, the CAS is banned (i.e. blocked) from receiving another read activation signal until a certain number of cycles (corresponding to the Ban #) has passed. The different settings are as follows:

tREF: Refresh Time. The amount of cycles between memory refreshes. Self explanatory. The higher this is, the more cycles between refresh command executions, i.e. the data is guaranteed to be stored for longer, but at the risk of degradation.


tMOD: MRS (Mode Register Set) Command to Non-MRS Command Delay. From what I can understand, DRAM modules contain a section of memory called the mode register, and it seems to have something to do with power states. At the very least, this timing seems to be related to tCKE, ProcODT, and RTT_NOM. To be more specific, it appears that the CKE state (LOW/HIGH) will only change if certain parameters are satisfied for at least tMOD + tMRD clock cycles.


tMODPDA: MRS (Mode Register Set) Command to Non-MRS Command Delay, Per DRAM Addressability Mode. Same as above regarding tMOD. Per DRAM Addressability Mode, or PDA, seems to save a single MRS value across a DIMM, which seems to have something to do with preventing data degradation.


tMRD: Mode Register Set Command Cycle Time. See tMOD.


tMRDPDA: Mode Register Set Command Cycle Time, Per DRAM Addressability Mode. See tMODPDA.


tSTAG: Subrefresh Staggering Delay. Seems to be related to tREF, in that it involves staggering memory refresh commands to minimize the amount of memory addresses that are being refreshed at any given moment.


tSTAGLR: It’s obviously related to tSTAG somehow, that’s all I know. It’s disabled for me, which may suggest it’s some kind of offset.


tPHYWRD: I believe this is related to a digital-to-analog microcontroller called a PHY chip found in the Ryzen SoC. This timing also appears to be related to writes.


tPHYWRL: Same as above.


tPHYRDL: Same as the two above, but related to reads.


tRDDATA: Probably related to data...wow.


tWRMPR: I have no idea.

Termination Resistances:


ProcODT
: Processor On-Die Termination Impedance. The resistance which a memory signal travelling to the CPU terminates at. This reduces signal noise and lowers how much the signal over- and undershoots the voltage that the signal should be sent at. From what I understand, going too low can allow signal noise to send faulty signals to the memory, but going too high can actually cause a signal to be absorbed and not reach the processor. This defaults to 53.3Ω.



RTT_PARK: Park On-Die Termination Impedance. The resistance at which signals sent to a memory die will terminate when ODT is low. I believe this is related to CKE LOW/Powerdown Mode. From what I can decipher, when RTT_NOM is disabled/off, this value seems to take over. This resistance can help prevent signal integrity loss to dies in which the memory is not executing write commands. The values for this are measured in terms of fractions of RZQ, which is a reference 240Ω resistor.


RTT_NOM: Nominal On-Die Termination Impedance. For high ODT, this is the termination resistance for signals sent to a memory die not being written to, but which is connected to one that is being written to. I believe this is related to CKE HIGH pulses. This resistance can help prevent signal integrity loss when the memory is not executing write commands. The values for this are also measured in terms of fractions of RZQ.



RTT_WR: Dynamic/Write On-Die Termination Impedance. This is the resistance at which signals sending write commands to a memory die will terminate at. This resistance can help prevent signal integrity loss when the memory is executing write commands. The values for this are also measured in terms of fractions of RZQ.



ClkDrv or CLKDrvStr(en): Clock Drive Strength/Impedance. The resistance on the MEMCLK (memory clock) drive pins on the CPU (or memory controller?). This adjusts the strength of the signal that controls memory clock. I believe this should have some effect on stabilizing memory frequency, and theoretically higher values may improve signal quality to the corresponding pin.



AddrCmdDrv or AddrCmdDrvStr(en): Address/Command Drive Strength/Impedance. The resistance on the following CPU (or memory controller?) pins: address, RAS, CAS, WE, bank, parity. Theoretically, then, raising it can increase stability of tight timings. However, I have not tested that specifically.



CsOdtDrv or CsOdtDrvStr(en): Chip Select/On Die Termination Drive Strength/Impedance. The resistance on the CS and ODT pins on the CPU (or memory controller?). This adjusts the strength of the signals controlling Chip Select (which is self explanatory) and ODT (which in this context is related to CKE and DRAM powerdown state). As before, raising might be helpful, but isn’t necessarily.



CkeDrv or CKEDrvStr(en): CKE (Clock Enable) Drive Strength/Impedance. The resistance on the CKE pins on the CPU (or memory controller?). This adjusts the strength of the CKE signal, which I discussed previously. As before, raising might be helpful, but isn’t necessarily.


CAD_BUS Timings:


AddrCmd(Setup): Address/Command Setup Time. The setup time for the address and command pins of the CPU (or memory controller?) with respect to a memory clock. Essentially, this prepares the address and command pins a fraction of a memory clock before a read or write command must be sent. If set to 0, then the pins will set up 1/2 of a clock before the command is sent for CR=1T or 1 1/2 clocks before the command is sent for CR=2T. If set to 1, the number of clock cycles for setup will equal your command rate.




CsOdt(Setup): CS/ODT Setup Time. The setup time for the CS and ODT pins of the CPU (or memory controller?) with respect to a memory clock. If set to 0, the pins will set up 1/2 of a clock before a read or write command is sent. If set to 1, they will set up 1 clock before.



Cke(Setup): CKE Setup Time. The setup time for the CKE pins of the CPU (or memory controller?) with respect to a memory clock. See CsOdt(Setup) for behavior.


Em nota de conclusao, nao há nenhum tutorial infalivel, tudo que vais encontrar na net sobre isto sao enganosos na melhor das hipoteses e perigosos na pior... o melhor que tens a fazer quando vais fazer oc á ram é perceberes no que estas a mexer e como isso pode afetar a estabilidade do teu sistema.

Vou ser franco, quem pergunta se há tutorias para fazer oc á memoria nao esta preparado para o fazer.

Abc
 
Obrigado pela resposta.
Tenho algumas luzes mas ainda estou muito verde... Mexer nos Timings principais já domino agora os sub Timings é uma comidela.
Cumprimentos
 

Websync

Power Member
Se tu ja tens as tuas memorias a 3800mhz cl16 os ganhos que vais ter a partir desse ponto tanto em latencia como velocidade vai ser sao minusculos que nao vais encontrar nenhum beneficio aparte de benchmarks,

Dito isto, se ainda achas que que vale a pena puxar por elas o mais perto dum tutorial que te posso recomendar é procurar pela internet que tenha feito OC num CPU similar ao teu, idealmente no mesmo chipset, com memorias iguais ás tuas, e usas isso como uma baseline para comecares.

Só para teres uma ideia, eu no meu ultimo OC demorei meses a conseguir ir de 3000mhz para 3600mhz num modelo c-die, é algo que requer paciencia.
 
Topo