Novos P4's + rapidos!

[SKATAN]

jackson technology = hyper-threading

nos velhos PIV diz que tmb suporta por isso só vão ver isso nas novas mobos e nos 3ghz


[edit]os novos piv c1 são mesmo brutais 3.2ghz para cima a ar nas puras e a 1.65v , 2600+ quê???? LOL[/edit]

 

[pnabais]

Reviews em:

http://www.tomshardware.com/cpu/02q3/020826/index.html

http://www.hothardware.com/hh_files/CCAM/p4_28g.shtml

http://www.simhq.com/simhq3/hardware/reviews/p42800/


http://tech-report.com/reviews/2002....8/index.x?pg=1

http://www.ocworkbench.com/2002/int...8g/p42.8gp1.htm

http://www.xbitlabs.com/cpu/p4-2800/

http://www.hexus.net/review.php?review=407

http://www.gamersdepot.com/hardware.../p4_2.8/001.htm


http://active-hardware.com/english/.../p4-2800mhz.htm

http://www.hardocp.com/article.html?art=MzQ4


http://www.hardware-unlimited.com/r...pentium-4-2800/

http://www.aceshardware.com/read.jsp?id=50000293

http://www.vr-zone.com/reviews/Intel/P42800/

http://www.viahardware.com/intel28_1.shtm

http://www.gamepc.com/labs/view_con...cookie_test=1

http://www.tweaktown.com/document.p...=review&dId=343

 

[Zealot]

Boas nabais. Não esperava outra coisa de um intelista como tu. É bom ver-te no activo.

 

[Crusher]

Dá que pensar heim?

"Thanks to Sampsa Kurri from the Finnish site Muropaketti.com for posting about the Pentium 4 iTLB. Apparently, the Pentium 4 has always had 128 instruction TLB entries, and not just the new stepping as reported in our review. This information is confirmed on page 364 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3:


Pentium 4 and Intel Xeon processors: 128 entries, 4-way set associative.
P6 family processors: 32 entries, 4-way set associative.
Pentium processor: 32 entries, 4-way set associative; fully set associative for Pentium processors with MMX technology.
According to Sampsa, there is a bug in older revisions of the Pentium 4 that mistakenly reports 64 entries instead of 128. This has been fixed in the newest stepping, causing WCPUID to report the correct value.

My friend told me that there is a bug in older Pentium 4 CPU steppings. EAX=0000_0002h register returns wrong value. (If Intel document is correct and there should be 128 entries).

If you look at this document and page 8:

http://www.intel.com/design/processor/future/manuals/Cpuid_supplement.pdf

This document tells what Descriptor values are for 64 entries, 128 entries and 256 entries. For some reason in older P4 stepping (B-0) EAX=0000_0002h returns value 50h but it should return value 51h.
So, the question is, if the TLB has not been changed, then what's responsible for the per-clock performance improvement of the new stepping? Upon contacting Intel, Sampsa was told there were no performance improvements in the new stepping, despite the fact that he has reported a 10 second improvement in SuperPi at the same clockrate. Indeed, our own benchmarks have indicated a 1 to 5 percent IPC increase in several benchmarks. We saw a 7 second improvement in ScienceMark 2.0's Moldyn benchmark and a 28 second improvement in Primordia, at the same clockrate.

We've contacted Intel for more information and we hope to have a response sometime today. As soon as we have it, we'll update both this post and our review with details."

http://www.aceshardware.com/

Pois é... pensava-se que Intel tinha mudado o steping do CPU para só alcançar mais velocidade, e que tinham aumentado o tamanho dos TLBs como aconteceu da passagem do TBird para o Palomino, e afinal era por causa do WCPuid que fazia o report errado dos P4 relativo aos TLBs.

Mas algo a Intel mudou para que o CPU desse mais clock a clock em relação aos "manos" mais velhos...

E esta hein?