Nemesis11
Power Member
Primeira noticia da IDF, que começa amanhã.
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=193005167
Press release - http://www.rambus.com/us/news/press_releases/2006/060925.html
SUNNYVALE, Calif. — A second-generation PCI Express controller and physical (PHY) interface developed by Rambus Inc. (Los Altos, Calif.) doubles the speed of the previous-generation PCI Express solution. Moving data at 5 Gbits/s, the Gen2 controller/PHY combination provides a complete communication interface solution that is fully backward-compatible and works with the 2.5-Gbit/s Gen1 PCI Express interfaces.
Available as a block of intellectual property, the controller can be used to implement root complex, switch port, endpoint and hybrid (endpoint/root complex combination) device types. The PHY can support either PMA (physical media attachment) or PCS (physical coding sublayer) layers of the transceiver. The interface to the data-link layer from the PHY complies with PIPE specification 2.0. The PMA macro consists of the serializer, transmitter, receiver, deserializer and clock-recovery circuitry. It also supports PCI Express power management and idle state controls. A separate reference clock buffer cell is also available to drive multiple PHY cells.
The controller portion handles the transaction, data link, and media access control layers of the PCI Express stack. To simplify and speed system integration, the company also offers optional tools and IP for direct connection to standardized on-chip system. Verification IP customized specifically for the digital controller enables automatic verification of the PCI Express stack in the system verification environment. As part of the controller IP, Rambus offers in-system self-diagnostic, channel and burst-error-rate tools to evaluate the in-silicon health of the PHY and digital controller. The self-diagnostic features include ac and dc JTAG boundary scan, serial and parallel loopback, scan and at-speed BIST support, and receive jitter-tolerance testing.
The controller/PHY combination can be configured for by-1, by-4, by-8 or by-16 lane implementations and can use 100-, 125- or 250-MHz reference clocks. Further, the IP can be targeted for 130-, 90-, 65- and 45-nm process geometries. For evaluation, the company offers a Gen2 PHY evaluation board that can demonstrate the key Gen2 PHY and controller functions.
http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=193005167
Press release - http://www.rambus.com/us/news/press_releases/2006/060925.html