Rambus targets DDR4 DRAMs
Ainda é só em 2011... Supostamente será para o Tok do Sandybridge, e início de nova arquitectura Intel...
Link: EETimesSAN JOSE, Calif. — Rambus has announced a set of new and existing interconnect technologies it says will meet the needs of main memory in 2011 and beyond. It hopes the industry adopts the techniques as part of a pending DDR4 DRAM standard. The concepts are promising, but a history of intellectual property disputes clouds the road to adopting them. Rambus is in litigation with three of the four top DRAM makers, one of the cases stretching into its ninth year.
Some of the IP issues originated in work on memory interconnects in the JEDEC group that defines next-generation DRAM standards, a group in which Rambus no longer participates. JEDEC executives--and a handful of the group's members—declined to comment on the status or outlook for DDR4.
As part of its announcement, Rambus outlined a handful of market requirements it believes will be key for main systems memory interconnects in 2011 and beyond. They include doubling today's DDR3 per-pin data rates to 3,200 Mbits/second, slashing active and idle power rates significantly and maintaining support for multiple dual in-line memory modules (DIMMs) per memory channel.
The company disclosed two new technologies as part of a new main memory initiative to address those requirements, module threading and a new single-ended version of its near-ground signaling technology.
As the name suggests module threading splits a link into two parallel threads. It aims to tap the significant unused bandwidth of a DDR3 link while cutting in half the power used to activate a row.
The two threads are generated by accessing a module on both the right and left side in an out-of-phase fashion and pipelining the data. Rambus has shown power reductions of 20 percent using module threading on a prototype DDR3 DIMM.
The other new technique--near ground signaling—was applied in a differential version in an ISSCC paper in February 2007. The new version uses single-ended signaling. It opens the door to use of power sources as low as 0.5V and 80 percent reductions in signaling I/O thanks to very low voltage swings.
As part of its main memory initiative, the company is packaging three of its existing technologies along with the two new ones. FlexPhase enables high data rates by overcoming the speed limitations of the direct strobing technology used in DDR3, Dynamic Point-to-Point technology is a signaling technique aimed to boost capacity and FlexClocking reduces clocking power by eliminating the need for a phase-locked loop on the DRAM.
The first two techniques are part of the Rambus XDR memory architecture. The latter technique was introduces as part of the company's mobile memory initiative announced in February.
Rambus claims that used in concert the five techniques can provide twice the bandwidth of a DDR3 link at nearly half the active power and a fraction of the idle power while still supporting multiple DIMMs per memory channel. The company will release a white paper on its Web site detailing the techniques.
Licensing--that's the rub
"The strategy is to develop the innovations, announce them and show their value to the industry [as] a way to improve industry main memory and fit in standard industry cost structures," said Michael Ching, director of strategic development at Rambus. "We are not proposing an entirely new architecture," he added. Rambus, working with Intel, did proposed a new architecture with its Rambus DRAMs introduced as a follow on to PC-133 memories several years ago. Memory makers pushed back on the approach which would have required them to pay Rambus royalties.
Rambus then sought royalties on what it claims were its technologies used in synchronous and double data rate DRAMs. Memory makers claimed Rambus failed to disclose its technologies during JEDEC meetings where the standards were set. A tangle of court case ensued, many of which are still ongoing today.
"Having our technologies adopted has never been a problem," said Sharon Holt, vice president of licensing and marketing at Rambus. "Our technologies have been used whether people have a license or not—that's the rub," she said.
The company has outstanding court cases with Samsung, Hynix and Micron. But "we have a track record of working with people even when litigation is going on," she added.
Indeed, Rambus has already started talks on its main memory initiative with chip set and DRAM makers as well as OEMs, said Herb Gephardt, vice president of strategic development at Rambus. "We're letting the industry know about our innovations at a time when the [DDR4] spec is being developed," he said.
JEDEC declined to comment on the status of the DDR4 standard. Intel also declined to discuss any talks on the interface which it will presumably use in its next-generation 32nm processor architecture called Sandy Bridge. The first members of that family are expected to ship in 2011. For its part, Samsung would only say it is "actively participating" in work on DDR4 and future memory technologies.
The DDR4 work comes at a time when NAND flash technologies such as Spansion's EcoRAM and new products from startup Schooner are encroaching on traditional DRAM applications, said Bob Merritt, principal analyst with Convergent Semiconductors (Monarch Beach, Calif.).
"DDR4 may take awhile to get defined because we will have to get a better idea of what the performance characteristics will be in the remaining apps for DRAMs," Merritt said. Defining a DRAM architecture "is just more complex this time," he added.
In addition, "a lot of road maps and plans are being pushed out due to the downturn," said Holt of Rambus. "It's possible there's been a slowdown in the normal cadence of things," she added.
Being part of the new spec is significant for Rambus which gets the lion's share of its revenues from licensing DRAM technologies. The company reported a net loss for the first three months of 2009 as well as for calendar 2008 and made a 21 percent cut of staff in August.
Ainda é só em 2011... Supostamente será para o Tok do Sandybridge, e início de nova arquitectura Intel...
