Motherboard Researchers Want to Ditch the Motherboard

JPgod

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University of California at Los Angeles researchers want to do the unthinkable: kill the motherboard. In a recent piece for IEEE Spectrum, the researchers said this act of technological matricide would enable the creation of more powerful systems that aren't constrained by the printed circuit board (PCB) used today, all thanks to a new silicon-interconnect fabric that can be used in the motherboard's stead.

https://www.tomshardware.com/news/r...rboard-silicon-interconnect-fabric,40475.html

Que acham disso?

Ainda que seja possível ir mais longe na integração, já passou do tempo de acabar com o chipset externo e integrar todo o I/O no CPU (só existe esta situação em alguns casos como Atons, o Epyc), mas dado que uma das funções das motherboards é a alimentação do CPU, memória, gráfica, etc como que é possível tal?
 
Acho que isso é mais importante para o mercado servidor. A ideia é ter "blocos", para depois se poderem criar pools com X de processadores, X de RAM, X de Storage, X GPUs, etc.
Basicamente, desagregar ao máximo, para ter o máximo de flexibilidade.

A Dell andou a mostrar o que se pode fazer com Gen-Z há uns tempos, que é algo que ajuda a esse objectivo de desagregar os componentes (Não substitui motherboards, nem PCBs, etc):

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In our Dell EMC PowerEdge MX review, we noted that it is a chassis designed for the Gen-Z future. At Dell Technologies World, Dell EMC showed off the Gen-Z future. Here is Gen-Z replacing one of the fabric modules in the PowerEdge MX and an external server outside of the chassis reading/ writing the same memory.

In a particular treat, I was able to see one of the prototype fabric modules.

One can see external cabling at the rear. Under the middle heatsink, one can see a Xilinx FPGA that makes Gen-Z possible. One can also see the connectors that connect this PCB to the individual nodes in the PowerEdge MX’s “no midplane” design. You can read more about that in our review.

If one then thinks of CXL as the protocol for in-chassis hardware such as local memory, storage, and accelerators and Gen-Z as chassis-to-chassis, one can understand how these co-exist and why Dell EMC and HPE are pushing both protocols. In the PowerEdge MX (MX7000) demo, we are seeing Gen-Z going from chassis to chassis.

Looking further into the future, I asked about how long until we see memory controllers being on the far side of the bus from the CPU. Memory controllers take up a lot of silicon on modern CPUs and the idea of using a high-speed link is one that has been around for some time. Barry and Kurtis were a bit less definitive here saying we may start to see this in the DDR5 generation.

https://www.servethehome.com/gen-z-in-dell-emc-poweredge-mx-and-cxl-implications/
 
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