Processador Risc-V

[Nemesis11]

Tirando os chineses a SiFive é de facto "A" RISC-V.

A nível de visibilidade, talvez, mas tens empresas como a Western Digital a apostar forte em Risc-V, internamente e até a nVidia usar Cores derivados de Risc-V, nas ultimas gerações de GPUs, para "management" interno.

Seja como for, onde queria chegar é que este negócio é muito diferente da compra da ARM. A SiFive é uma Startup, tem produtos directamente para o consumidor final e não tem qualquer exclusividade sobre o ISA.

Um video do Ian sobre a notícia:

 

[Dark Kaeser]

Sim a WD tem Risc-v mas é para controladores, não vejo o interesse da Intel nisso.

Diferente seria a Intel apostar no RISC-V para consolidar o "não x86", eles usam ARM nos FPGA e acho que ainda os MIPS na Mobileye.

Eventualmente outros produtos custom, para ocupar o IDM 2.0

 

[Dark Kaeser]

Intel to Create RISC-V Development Platform with SiFive P550 Cores on 7nm in 2022​

The new SiFive Performance P550 core at the heart of Horse Creek is SiFive’s highest performance processor to date, with the company quoting a SPEC2006int of 8.65 per GHz. It is a Linux-capable core, with full support for the RISC-V vector extension v1.0rc. It has a 13-stage triple-issue out-of-order microarchitecture with a private 32KB+32KB L1 cache and a private L2 cache (per core) The design supports four cores in a single cluster that can be paired up to 4 MB of shared L3.

The time scale for this platform coming to market is quite interesting. Despite Intel recently committed to bringing its 7nm to market in 2023 with the compute tile for its Meteor Lake processor as its first 7nm product, we’re being told that Horse Creek silicon will be ready in 2022, which would make Horse Creek its first 7nm product. For what it is worth, it’s unlikely that the Intel RISC-V solution is tile-based, but it might be easy enough to bring a small RISC-V chip development platform to market around then.

https://www.anandtech.com/show/1678...latform-with-sifive-p550-cores-on-7nm-in-2022

SiFive Performance P550 Core Sets New Standard as Highest Performance RISC-V Processor IP​

https://www.sifive.com/press/sifive-performance-p550-core-sets-new-standard-as-highest

 

[Dark Kaeser]

https://twitter.com/i/web/status/1415380378043486212

 

[muddymind]

Comparar com cortex-A75 quando actualmente temos o cortex-A78 e X1 e brevemente o cortex-A710 e X2?

 

[Dark Kaeser]

Russia To Build RISC-V Processors for Laptops: 8-core, 2 GHz, 12nm, 2025

conglomerate Rostec, a Russian state-backed corporation specializing in investment in technology, has penned a deal with server company Yadro and silicon design company Syntacore to develop RISC-V processors for computers, laptops, and servers. Initial reports are suggesting that Syntacore will develop a powerful enough RISC-V design to power government and education systems by 2025.

https://www.anandtech.com/show/1682...-processors-for-laptops-8core-2-ghz-12nm-2025

 

[Dark Kaeser]

Lá vão começando a aparecer...

Chinese Academy of Sciences released the domestic RISC-V processor "Xiangshan", which has successfully run Linux, and will be released in July​

June 11, 2020, Xiangshan established a code repository on GitHub.

Afterwards, Xiangshan's research and development progressed very fast: on July 6th, the out-of-order pipeline was completed and CoreMark was able to run correctly; on September 12th, Linux started correctly; on October 22nd, Debian started correctly.

The "Yanqi Lake" RTL code was completed in April this year, and it is planned to be taped out in July based on TSMC's 28nm process.

The second-generation architecture is called "Nanhu" and will use SMIC's 14nm process. It is expected to be taped out by the end of this year.

Performance parameter

"Yanqi Lake" adopts out-of-order execution, 11-level flow, and 6-launch. Due to the use of the older 28nm TSMC process, the main frequency is low, and it is expected to reach 1.3Ghz.

The performance score of "Yanqi Lake" SEPC2006 is about 7/Ghz. From this point of view, Xiangshan's first-generation architecture mainly targets ARM's A72 or A73.

The second-generation architecture has greatly improved performance. Bao Yungang said that the goal of "South Lake" is for SEPC2006 to reach 20 points, which is 10/Ghz, which is close to the 11.08/GHz of i9-10900K.

https://min.news/en/tech/022cca805c...c9c7e0b3cd5-1626806874-0-gqNtZGzNAk2jcnBszQY6

XiangShan open-source 64-bit RISC-V processor to rival Arm Cortex-A76​

This culminated with an 8-core prototype built based on Yanqihu (雁栖湖) architecture using TSMC’s 28nm process with the processor running up to 1.2 or 1.3 GHz that should be taped out this month. But plans have been made to tape out a new prototype based on Nanhu (南湖) by the end of the year, using SMIC’s 14nm process allowing up to 2 GHz frequency, and further iterations of the architecture will aim at rivaling Arm’s Cortex-A76 processor.

https://www.cnx-software.com/2021/0...64-bit-risc-v-processor-rival-arm-cortex-a76/

 

[Dark Kaeser]

Este ultimamente tem andado a fazer muitas experiências, começa a ficar com uma colecção notável.

Última aquisição

https://twitter.com/i/web/status/1438525014345584649

 

[Nemesis11]

Os primeiros samples do Processador Europeu para HPC.

The test chip, shown in the figure below, contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The chip also includes two additional accelerators: the Stencil and Tensor accelerator (STX) designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. All accelerators on the chip are connected with a very high-speed network on chip and SERDES technology from EXTOLL.

The 143 packaged EPAC test chip samples were fabricated in GLOBALFOUNDRIES 22FDX low-power technology, have an area of 26.97mm2, 14 million placeable instances (93M Gate Equivalent) including 991 memory instances, are packaged in FCBGA with 22×22 balls and have a target frequency of 1GHz.

EPI will continue to develop, optimize and validate different IP blocks and demonstrate features and performance of those thus creating an EU HPC IP ecosystem and make it available to the processor and accelerator industry and academia to create globally competitive production class building blocks for the next generation HPC systems.

https://www.european-processor-initiative.eu/epi-epac1-0-risc-v-test-chip-samples-delivered/

 

[Dark Kaeser]

Hmm 28nm FDSoi?
Escolha de processo um pouco estranha.

 

[Nemesis11]

Benchmarks iniciais do HiFive Unmatched

For those wanting to experiment with RISC-V hardware today, SiFive's HiFive Unmatched is currently the best developer platform to do so with there not being any other similar solution available at this time. The HiFive Unmatched is quite capable even as a RISC-V developer workstation with having 16GB of RAM and support for Radeon open-source graphics with a compatible dGPU, NVMe storage, and plenty of other connectivity options.

Those interested in learning more about the HiFive Unmatched or ordering one can find all the details at SiFive.com. Thanks to SiFive for supplying this review sample and stay tuned for more benchmarks of it as the Linux/open-source RISC-V software continues to evolve as seen from Ubuntu 21.04 to 21.10 while things are only heating up for this open-source processor ISA.

https://www.phoronix.com/scan.php?page=article&item=hifive-unmatched-benchmarks
Muitos outros Benchmarks com esta plataforma -> https://openbenchmarking.org/result/2109248-TJ-SIFIVERIS17

Ainda há um longo caminho a fazer a nível de software e hardware, o que é normal.

 

[muddymind]

 

[muddymind]

6,000 RISC-V Cores on a Xilinx FPGA Break the CoreScore World Record

 

[Dark Kaeser]

Isso no fundo é apenas a "simulação" no FPGA, que depende obviamente da ISA/complexidade core e do tamanho do FPGA, há algumas empresas a fazer isso, este artigo também é de ontem

Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation.​

he MCU family of RISC-V processors provides FPGA users with a fully RISC-V ISA compliant processor subsystem that requires less than 2000 LUTs on Xilinx devices, saving valuable on-chip resources for engineers to implement their proprietary logic.

Bluespec’s RISC-V MCU includes a pre-built open-source toolchain and reference designs for the Digilent® Arty Artix-7 FPGA Development board providing a low barrier path to begin developing their application in minutes with a professionally implemented, optimized, and verified RISC-V processor on Xilinx FPGAs.

https://www.design-reuse.com/news/50672/bluespec-risc-v-processor-ilinx-fpga.html


Mais interessante parece ser o recente anúncio de uma startup que fez $38M numa ronda de financiamento, a aposta em chiplets e foco em servidores

Ventana Sees Window for Robust RISC-V Server Business​

Armed with $53 million in capital — including quiet early investments from Cisco, which has been a partner since the beginning — Venta marched out of stealth this week with recognizable veterans, including Greg Favor, who was one of the forces behind the AMD K6 architecture before moving through a few startups and landing at Applied Micro and then Ampere (which itself spun out of Applied).

Co-founder and CEO Balaji Baktha also has a long background in architecture, although most frequently and recently on the investment side. In 2010, he founded Veloce Technologies, which aimed to create the first 64-bit Arm processor. This company was acquired by Applied in 2017 and Baktha says much of this technology helped Applied Micro spin out its own Arm processor, which later translated into elements of Ampere’s technology.

Ventana delivers its IP in a 16-core CPU cluster in 5nm as a known good die in chiplet form à la AMD. “We prove everything in 5nm and give customers a fully functioning silicon device. They can glue that chiplet to their SoC using a standards-based parallel interface that can allow them to rapidly productize an SoC.”

Users can decide what they want that chiplet to emphasize (different memory sizes, PCIe lanes, etc). The major feature is that the high-speed parallel interface (which they provided no details about) is that it appears native to the CPU core. That means architects can add accelerators that operate at silicon speed instead of working in a staged pipeline through PCIe.

As of this week, the company raised yet more capital with $38 million in a Series B funding round. The round was led by Dr Sehat Sutardja and Weili Dai (founders of Marvell Technology Group) and other prominent semiconductor investors in partnership with Series A investors — which include that notable strategic partner, Cisco — bringing Ventana’s total funding to $53 million.

https://www.nextplatform.com/2021/09/02/ventana-sees-window-for-robust-risc-v-server-business/

RISC-V Chiplet Startup Raises $38M, Targets Data Center Compute​

EE Times spoke to one of the founders, Balaji Baktha, to get some more background and it became clear this was more than just another RISC-V project. He and his co-founder and Greg Favor both have a strong track record in data centers, CPU architectures and network processors. Baktha emphasized his work on several generations of data centers, with companies like Marvell, Adaptec, and Veloce Technologies; and Favor’s work with successful server class x86, Arm 64-bit CPUs and network processors, through key roles at AMD, Ampere, Sierra Systems, and Montalvo.

In addition to their own track record, Ventana also has prominent investors behind it who believe its new approach could be “revolutionary.” This series B round led by Marvell founders Sehat Sutardja and Weili Daiits takes its total funding to date to $53 million, with other unnamed semiconductor industry investors (however, SEC filings indicate directors with strong background in system architecture at Cisco and MIPS).

https://www.eetasia.com/risc-v-chiplet-startup-raises-38m-targets-data-center-compute/

e um artigo do CEO no EETimes

Chiplet Strategy is Key to Addressing Compute Density Challenges​

https://www.eetimes.com/chiplet-strategy-is-key-to-addressing-compute-density-challenges/

 

[muddymind]

Tantos desenvolvimentos em RISC-V há já algum tempo e no entanto ainda não temos uma implementação menos exótica com músculo de jeito...

Ainda tinha alguma esperança no HiFive Unmatched mas acabaram atropelados por ARM nos raspberry pis... O que falta mesmo para isto descolar de uma vez? Várias empresas mostram interesse mas isto não sei nem por nada lol.

 

[Dark Kaeser]

Diria que, tal como está no artigo acima e na primeira pessoa por quem experimentou isso na pele:

It has been a tough slog for Arm server technologies to reach anything near mass market. So what changed or is shifting now to make this different?

The market wasn’t ready for the Veloce 64-bit Arm technology, and Baktha says this gave him insight on how to prepare for more fertile ground.

“When we started, TSMC was the only fab we could use and was two process nodes behind Intel. To try to compete at that disadvantage as a problem. Also, the software ecosystem investments from Arm were not adequate. They didn’t put a lot of money to work and couldn’t push the ecosystem forward. That work was left to the silicon folks at Applied and Qualcomm for example.”

https://www.nextplatform.com/2021/09/02/ventana-sees-window-for-robust-risc-v-server-business/

Tirando os microcontroladores RV32 (32 bits), que constitui o grosso do uso do Risc-V, tens o resto no embedded (RV32 e RV64), no qual se inclui a HiFIve e muitos outros, mas destes poucos estão acima, essencialmente a SiFive e a T-Head
https://riscv.org/exchange/cores-socs/

a maioria das boards disponiveis são praticamente abaixo das SiFive e Allwiner (que na realidade são os T-Head licenciados).
A T-Head sendo parte de um grupo chinês da cloud resta saber se irão comercializar os ditos (fora de sistemas), e tens uns Russos que vão produzir para o governo logo duvido que se preocupem com a performance ou consumos.

Tirando o Esperanto ET-SoC-1, para AI e este acima, a maioria é projectos "académicos" como o EPAC (post do Nemesis11), Xiangshan (post meu sobre projecto chinês) e outro da DARPA (projecto académico)


A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

The project is part of the DARPA Circuit Realization At Faster Timescales (CRAFT) program which wants to drive the design cycle for custom integrated circuits to weeks and months from years.

As a quick overview of the entire Celerity SoC, it’s a many-core multi-tier AI accelerator. At a high level, the chip comprises three main tiers – general-purpose, massively parallel, and specialization. Why a tiered SoC? To enable both high flexibility and higher power efficiency over a typical CPU design (albeit not quite as efficient as ASIC NPU). The general-purpose tier can pretty much do anything – general compute, memory management, and control the rest of the chip. For this reason, they have integrated five high-performance out-of-order RISC-V Rocket cores from the Free Chip Project. The next tier over is the massively-parallel tier which integrates 496 low-power custom-designed RISC-V cores in a mesh.

https://fuse.wikichip.org/news/3217/a-look-at-celeritys-second-gen-496-core-risc-v-mesh-noc/
https://riscv.org/wp-content/upload...e-RISC-V-Tiered-Accelerator-Fabric-Taylor.pdf

Só de há um ano para cá é que se tem visto alguma contribuição consistente para o kernel linux, e na maioria por parte da SiFive e T-head, que é uma parte importante para a "massificação" da coisa.
De resto como já disse algures mais atrás, os chineses já tinham portado e conseguiram pôr o Android 10 num T-Head.

 

[Nemesis11]

Tantos desenvolvimentos em RISC-V há já algum tempo e no entanto ainda não temos uma implementação menos exótica com músculo de jeito...

Ainda tinha alguma esperança no HiFive Unmatched mas acabaram atropelados por ARM nos raspberry pis... O que falta mesmo para isto descolar de uma vez? Várias empresas mostram interesse mas isto não sei nem por nada lol.

Tudo normal. O ISA é extremamente recente, tem uma licença que permite enorme fragmentação e penso que ainda há partes do Spec que não são finais.
Aqueles Dev Kits não são para o Consumidor Final. Aquelas Boards terão uma produção limitada e têm como objectivo amadurecer a plataforma, especialmente a nível de software.
É "engraçado" ver resultados, mas não têm grande significado. O Preview do Phoronix, tem uma página com resultados entre o Ubuntu 21.04 e o 21.10. Este ultimo, na altura, nem em Beta estava.
Em menos de 6 meses, todos os resultados tiveram melhorias e são saltos grandes. O que teve menor salto foi de 6,6 % e estão lá muitos com saltos de 20% ou mais.

No mercado consumidor, não espero nada competitivo a nível de Performance nos próximos anos. Por enquanto, é apenas interessante de acompanhar.

 

[Nemesis11]

Intel Infuses Nios Soft Processors with RISC-V Instruction Set​

Intel updated its lineup of the famous Nios soft processors with the latest Nios V softcore, designed around the open-source RISC-V instruction set architecture.

The Nios family of processors is Intel's implementation of simple low-power processors designed to fit inside Field Programmable Gate Array (FPGA) designs and occupy just a tiny portion of it, supplying basic CPU functionality. According to Gartner, the Nios CPU family is the most widely-used softcore tech in the FPGA industry. These soft cores allow FPGA designs to have the basic functionality that the design would require from a CPU. This way, the company provides hardware designers with basic CPU needs with their Intel FPGAs, enabling faster hardware development.

For now, the Nios V is a microcontroller in the V/m form. This design uses the RV32IA part of the RISC-V specification with atomic extensions, a 5-stage pipeline, and AXI4 interfaces, creating a capable microcontroller design. However, Intel plans to continue engineering Nios V design IPs and develop a Linux-capable V/g general-purpose Nios V form of processor capable of running Linux kernel.

The introduction of Nios V means that Intel is finally jumping on the RISC-V open-source bandwagon. The company already offers some of the first designs based on the open ISA, and in the future, we could see more powerful designs emerge from Intel's design centers.

https://www.tomshardware.com/news/intel-updates-soft-cores-with-risc-v

São Soft Cores para serem usados em FPGAs.
Não me parece inocente o uso de Risc-V por parte da Intel.

 

[Dark Kaeser]

Isso deve ser semelhante às implementações em Verilog, mas não deixa de ser interessante esta escolha da Intel.

 

[Nemesis11]

Entretanto parece que as negociações entre a Intel e a Sifive, para a sua compra, caíram por terra. Não rejeitam novas negociações com a Intel ou outras empresas, mas vão planear seguirem o caminho de uma IPO.

Intel’s Talks for Chip Designer SiFive Have Ended Without a Deal​

Intel Corp.’s talks with chip designer SiFive Inc. have ended without a deal and the startup will seek outside investment instead, according to people with knowledge of the matter.

Talks between the two companies fell apart recently after they couldn’t agree on financial terms and how the SiFive technology would be integrated into Intel’s chip roadmap, the people said, asking not to be identified because the matter is private.

SiFive is now looking to stay independent and sees an eventual initial public offering as a long-term goal, they said.

While the talks have ended, SiFive hasn’t ruled out eventually returning to discussions with Intel or other parties, the people added. The company had fielded takeover interest from Intel and other suitors earlier this year, Bloomberg News previously reported.

Representatives for Santa Clara, California-based Intel and San Mateo, California-based SiFive declined to comment.

SiFive plans to increase hiring next month for its division that designs CPUs, or central processing units, one of the people said. The company aims to grow its CPU team from 200 to 400 employees. SiFive is working on chips that can compete with the high-end designs developed by Arm Ltd.

The chip industry is made up of two primary chip architectures: X86 and Arm. The X86 technology is currently used by Intel processors while Arm powers much of the mobile world including chips developed by Apple Inc. and Qualcomm Inc. SiFive is a leading developer of RISC-V technology, a newer architecture that’s starting to catch on.

RISC-V is seen as an attempt to bring open-source standards to chip designs, which could make such technology cheaper for chipmakers. Interest in SiFive increased after Nvidia Corp. announced a deal to buy Arm, which like SiFive, licenses chip and process designs. There are fears within the technology industry of Arm becoming less collaborative if its deal with Nvidia closes.

SiFive Chief Executive Officer Patrick Little is a chip industry veteran. He joined SiFive last year from Qualcomm Inc. where he was a senior vice president in charge of their automotive business.

https://www.bloomberg.com/news/arti...chip-designer-sifive-said-to-end-without-deal


A Sifive também apresentou hoje um teaser de um novo Core Risc-V, que acho que ainda não tem nome, alegadamente mais rápido que o A78 da ARM.

https://www.hardwareluxx.de/index.p...auf-den-nachfolger-des-risc-v-p550-kerns.html