Processador Risc-V

[Dark Kaeser]

Há uma nova versão do Allwiner D1, o D1s que é versão "low cost", perdendo algumas coisas face ao D1 "normal".

Allwinner D1s/F133 RISC-V processor integrates 64MB DDR2​

Allwinner D1s (aka F133) is a cost-down version of Allwinner D1 RISC-V processor introduced earlier this year together with a Linux capable development board, with the main difference being the integrated 64MB DDR2.

Besides the built-in RAM, Allwinner D1s comes with many of the same features as D1 RISC-V SoC, but loses HDMI output and the HiFi 4 audio DSP, and Allwinner made some tweaks to the IOs with one less I2S audio interface, and general-purpose ADC.

https://www.cnx-software.com/2021/10/25/allwinner-d1s-f133-risc-v-processor-64mb-ddr2/

 

[Dark Kaeser]

https://twitter.com/i/web/status/1455946642406842369

Acho que foi na conferência Linux Foundation Member Summit... não encontro mais nada.

 

[Dark Kaeser]

Tenstorrent CTO Jim Keller talks about the future of building AI silicon at Samsung Foundry's SAFE '21 Conference.

"Building for the future is really about modular, provable design. The way to build high-performance chips is you have to get the details right, but then the pieces really have to go together. And the result of that is a system that's easy to build and you can do it with a smaller team and make progress. We think the next five years of AI is going to be a massive amount of innovation, both around the processors, the algorithms and how the chips work together." - Jim Keller

 

[muddymind]

https://www.techpowerup.com/289543/...st-in-class-sifive-performance-p650-processor

Novo CPU P650 da SiFive

 

[Dark Kaeser]

RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs​

today announced that RISC-V members have ratified 15 new specifications – representing more than 40 extensions – for the free and open RISC-V instruction set architecture (ISA). Most notably, RISC-V members ratified the Vector, Scalar Cryptography, and Hypervisor specifications which will help unlock new opportunities for developers creating RISC-V applications for artificial intelligence (AI) and machine learning (ML), the Internet of Things (IoT), connected and autonomous cars, data centers, and beyond.

The RISC-V Vector specification will help accelerate the computation of data intensive operations like ML inference for audio, vision, and voice processing. With RISC-V Vector, developers can process complex data arrays and scalar operations quickly and with low latency. The simplicity and flexibility of Vector allows companies to easily customize RISC-V solutions for a wide variety of edge computing applications from consumer IoT devices to industrial ML applications.

The RISC-V Hypervisor specification virtualizes supervisor-level architecture to efficiently host guest operating systems atop a type-1 or type-2 hypervisor. Virtual machine implementations require the RISC-V Hypervisor specification. The Hypervisor specification will help drive RISC-V adoption in cloud and embedded applications where virtualization is critical, such as in data centers, automotive applications, and industrial control applications. The RISC-V community has ported KVM and other open source Virtual Machines on top of simulators using the new specification.

The RISC-V Scalar Cryptography specification enables the acceleration of cryptographic workloads for small footprint deployments. These extensions significantly lower the barrier to entry for secure and efficient accelerated cryptography in IoT and embedded devices.

https://riscv.org/announcements/2021/12/riscv-ratifies-15-new-specifications/

Parece alinhar com o tal roadmap apresentado ali acima.

 

[blaster_00]

Esse Tenstorrent com o Keller à frente é de acompanhar, não me admirava que viesse algo revolucionário daí e que a Tesla metesse isso nos carros.

 

[Nemesis11]

Ainda não vi o vídeo, mas a Tesla desenha os seus próprios chips para AI.

 

[muddymind]

Sim, a tesla investiu no seu próprio design e deixou de usar SoCs da nvidia. Supostamente as soluções da tesla são monstro em eficiência para o workload deles.

 

[blaster_00]

Sim, o Keller passou por lá, não me admirava que a Tesla comprasse a tecnologia ou IP se a tenstorrent fizer algo de inovador

sidenote: substituiram a nvidia pela intel e agora pela AMD
https://thedriven.io/2021/11/29/new-tesla-model-y-performance-gets-super-fast-amd-ryzen-chip/

 

[muddymind]

Mas isso é para o infotainment e não para inferência

 

[blaster_00]

yup, daí ser sidenote. O Keller trabalhou no AI quando lá esteve.

 

[Dark Kaeser]

Para o sector auto ja6 há uns chips com Risc-V, a Renesas este ano assinou um acordo com a SiFive, a única empresa com um SoC em que também usam um Risc-V, é a Kneron

https://www.allaboutcircuits.com/ne...-level-1-and-level-2-autonomy-to-any-vehicle/

 

[Nemesis11]

yup, daí ser sidenote. O Keller trabalhou no AI quando lá esteve.

O Keller trabalhou em muitas empresas importantes. DEC (agora HP), PA Semi (Agora Apple), AMD, Intel, Broadcom. Não quer dizer que, se um dia a Tenstorrent for vendida (E ele queira ir no "pacote"), seja comprada por uma destas empresas ou pela Tesla.
AI é um mercado muito recente e como ainda não houve uma consolidação, tem centenas de Players em muitas áreas. O futuro da Tenstorrent é uma incógnita.

 

[blaster_00]

O Keller ou é um óptimo profissional ou um lucky charm do caraças, em tudo em que se envolve sai alta performance

 

[muddymind]

A imagination agora também com cpus RISC-V

https://www.techpowerup.com/289656/imagination-launches-risc-v-cpu-family

https://www.anandtech.com/show/17104/imagination-launches-catapult-family-of-riscv-cpu-cores

 

[Dark Kaeser]

​

Staff Firmware Engineer - dGPU Security - 126062​

Specifically, within the Security group, the dGPU Platform Secure Group is responsible for the Security Stack that runs on the entire range of AMD Graphic Cards (Discrete GPUs) which include Consumer/Gaming, Datacenter and Server, enabling our customers to build driven solutions and driving the next innovation in ExaScale computing.

There will be opportunities to become a specialist in ARM and RISC-V Firmware Development, Bootloader development, RTOS, Cryptography, GPU to GPU communication, GPU Virtualization and Data Center solutions, as well as Pre-Silicon development environments such as Simulators, FPGAs and Emulation Platforms.

https://jobs.amd.com/job/Markham-Staff-Firmware-Engineer-dGPU-Security-126062-Onta/815041100/

È sabido que a AMD usa IP ARM (um ARM A-5) designado por Trustzone em alguns chips para funções de "security", aparentemente poderá também vir a usar Risc-V.

 

[Dark Kaeser]

E4 announces breakthrough innovative technologies spanning silicon, software and power management tools, integrated in the RISC-V based “Monte Cimone” cluster​

• Introducing Monte Cimone, a 6-node cluster integrating RISC-V processors, system software, power management tools

CINECA, the leading italian supercomputing center, has ported high-performance mathematical libraries (OpenBLAS, FFTW, Netlib-LAPACK, Netlib-scaLAPACK) and scientific applications (HPL, Quantum Espresso) against the RISC-V ISA supporting E4 and Università di Bologna in the validation of the components of the cluster in the operational environment.

The key hardware components of Monte Cimone are:

• 6 dual-board servers, with a form factor of 4.44 cm (1 Rack Unit) high, 42.5 cm width, 40 cm deep. Each board follows the Industry Standard Mini-ITX form factor (170 mm per 170 mm);
• Each board features one SiFive Freedom U740 SoC, 16 GB of 64-bit DDR memory operating at 1866s MT/s and high-speed interconnects with PCIe Gen 3 x8 operating at 7.8 GB/s, one Gigabit Ethernet, and four USB 3.2 Gen 1;
• In RV007 system the M.2 M-key expansion slot is occupied by a 1 TB NVME2280 SSD Module storage device used by the Operating System. The Micro SD card is present and used for the UEFI Boot;
• Two 250 W power supplies are integrated inside the case to support the current hardware and future PCIe accelerators and expansion boards;
• Integrated fans

Monte Cimone will be used as a platform for porting and tuning HPC-relevant software stacks and HPC applications to the RISC-V architecture.

https://www.e4company.com/en/2021/1...ted-in-the-risc-v-based-monte-cimone-cluster/

 

[Dark Kaeser]

Entretanto os chineses do Instituto de Computação ligado à Academia de Ciências apresentaram há dias o "novo" CPU - Nanhu.

https://static.sched.com/hosted_files/riscvsummit2021/8c/XiangShan-Yungang-Bao-20211206.pdf

 

[Dark Kaeser]

Ainda relacionado com a Risc-V summit, aparentemente os chineses da StarFive também têm praticamente pronto um "high-performance" core - "Dubhe".

StarFive Starts Delivery of High Performance RISC-V CPU Core IP “Dubhe”​

At RISC-V Summit 2021, StarFive Technology Co., Ltd. (hereinafter “StarFive”), the leader of RISC-V software and hardware ecosystems in China, announced the official delivery of the world’s highest-performance RISC-V CPU Core IP, codenamed “Dubhe”, to its customers.

As a 64-bit high performance CPU Core IP based on RISC-V, Dubhe offers the most complete instruction sets so far, including RV64GC, B (Bit Manipulation), N (User-Level Interrupts), and instruction sets needed for high-performance computing, including V (Vector 1.0) and H (Hypervisor). Dubhe is a super scaler design with deep out of order execution, and is highly optimized for performance.

According to customer evaluations, the working frequency of Dubhe can reach 2GHz@TSMC 12nm, with SPECint2006 of 8.9/GHz, Dhrystone of 6.6 DMIPS/MHz and CoreMark of 7.6/MHz. Customers have expressed that Dubhe is an ideal processor core to meet their requirements in new products.

https://www.eetimes.com/starfive-starts-delivery-of-high-perofrmance-risc-v-cpu-ip-core-dubhe/

Assim de repente pelos dados do SPEC 2006 8.9/Ghz, parecem estar ao nível do "core" da 2ª geração da Academia de Ciências Chinesa, do post acima, num processo da TSMC equivalente.
Dado que este artigo refere o SPEC 8.9/GHz e que o SoC terá 2.0GHz, então o SPEC 2006 total será 2x8.9 = 17,8 sendo que o da Academia Chinesa terá ~20.


E ainda um Rack Cluster com boards HiFive da SiFive

A Closer Look at the SiFive RISC-V Rack Cluster​

SiFive collaborated with AB Open to create a rack-mount RISC-V cluster based around the SiFive HiFive Unmatched developer platform for compute and a SiFive HiFive1 Rev. B development board for control.

Typical use cases​

The cooling fans are reasonably quiet and the cluster could equally be installed in an office rack or a data centre, providing a solution that is much more convenient than boards fitted into multiple off-the-shelf PC enclosures or secured directly to rack cabinet shelves.

The are many potential uses for the rack-mount cluster and these range from RISC-V software development and test, through to build farms and even scale out to enable proof-of-concept of larger designs that utilise SiFive Essential U74 processor cores.

https://abopen.com/news/a-closer-lo...rce=twitter&hss_channel=tw-722914767636004865


E ainda a Intel OneDNN adiconou o suporte à ISA RiSC-v

Intel's oneDNN Deep Neural Network Library that is part of their oneAPI toolkit is out with version 2.5 and brings RISC-V CPU support among other updates.

Intel's oneDNN library that helps developers build out deep learning applications continues to support more operating system platforms and hardware architectures. While obviously catering to Intel's own CPUs/GPUs, oneDNN has also built up support for AArch64, POWER, IBM Z, NVIDIA GPUs, and now with oneDNN 2.5 is even RISC-V processor ISA support.

https://www.phoronix.com/scan.php?page=news_item&px=Intel-oneDNN-2.5

 

[Dark Kaeser]

RISC-V-based System on Chip Developed by Finnish Consortium​

The first System on Chip (SoC) developed by the Finnish SoC Hub consortium has been taped out. The project partners will focus next on improving the design, automation and performance of the SoC. The first of the three chips to be developed by the consortium will be ready for deployment in early 2022.

The SoC Hub initiative, coordinated by Tampere University, Finland, and Nokia, was launched last year.

One of the key goals of the SoC Hub project is to enable rapid prototyping for new ideas, for example, in the Internet of things (IoT), machine learning and 5G and 6G technologies in silicon.

The chip is manufactured using TSMC’s recent 22nm Ultra Low Leakage process, which is especially well suited for IoT and Edge devices. Ballast contains several different RISC-V CPU cores, a Digital Signal Processor, an AI accelerator, rich sensor-like interfaces and an extension interface to FPGA. A full software stack – including drivers, software development tools and chip debugging support – has also been implemented. The chip supports both real-time operating systems and Linux simultaneously.

Besides the development of the SoC, the first phase of the project was also a major undertaking, involving building the consortium and the preparation of the necessary software and license agreements. Headed by Tampere University and Nokia, the consortium comprises CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec as partners.

https://www.hpcwire.com/off-the-wire/risc-v-based-system-on-chip-developed-by-finnish-consortium/