Processador Risc-V

[Dark Kaeser]

Entretanto já foi feito o upload de boa parte das apresentações da RISC-Summit, vou deixar aqui os da Esperanto e da XiangShan


- Accelerating AI and non-AI Workloads with 1000+ Energy-Efficient RISC-V Cores on a Single Chip - Art Swift, Esperanto Technologies

- XiangShan: an Open-source High-performance RISC-V Processor - Yungang Bao, Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)

o resto podem ver aqui

https://www.youtube.com/c/RISCVInternational/videos

 

[Dark Kaeser]

Mobileye Announces EyeQ Ultra: A Level 4 Self-Driving System In A Single SoC​

https://www.anandtech.com/show/17165/mobileye-announces-eyeq-ultra-l4-auto-soc

 

[Dark Kaeser]

Nada de muito novo...

Intel Launches $1 Billion Fund to Build a Foundry Innovation Ecosystem​

the fund will prioritize investments in capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, innovative chip architectures and advanced packaging technologies. Intel also announced partnerships with several companies aligned with this fund and focused on key strategic industry inflections: enabling modular products with an open chiplet platform and supporting design approaches that leverage multiple instruction set architectures (ISAs), spanning x86, Arm and RISC-V.

Intel is joining forces with leading partners in the RISC-V ecosystem, including Andes Technology, Esperanto Technologies, SiFive and Ventana Micro Systems. IFS plans to offer a range of validated RISC-V IP cores, performance-optimized for different market segments. By partnering with leading providers, IFS will optimize IP for Intel process technologies to ensure that RISC-V runs best on IFS silicon across all types of cores, from embedded to high-performance. Three types of RISC-V offerings will be made available:

• Partner products manufactured on IFS technologies.
• RISC-V cores licensed as differentiated IP.
• Chiplet building blocks based on RISC-V, leveraging advanced packaging and high-speed chip-to-chip interfaces.

https://www.intel.com/content/www/u...-fund-build-foundry-innovation-ecosystem.html

 

[Dark Kaeser]

Para o caso de alguém precisar...

https://twitter.com/i/web/status/1503755066347597831

Já agora a SiFive vendeu a parte de "conectividade" por 210M$

Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash​

Alphawave IP Group plc (“Alphawave” or “Company”) (LN:AWE), a global leader in high-speed connectivity for the world’s technology infrastructure is pleased to announce the acquisition of the entire OpenFive business unit from SiFive Inc. (“SiFive”). SiFive is the founder and leader of RISC-V computing based in San Mateo, California. All definitive agreements have been completed and the transaction is expected to close in H2 2022 pending customary regulatory approvals.

https://www.awaveip.com/en/news-vie...usiness-unit-from-sifive-for-us-210m-in-cash/

 

[Dark Kaeser]

Esperanto Technologies’ RISC-V AI Inferencing Solution Now in Initial Evaluations​

speranto Technologies, a leading developer of high performance, energy-efficient artificial intelligence (AI) inference accelerators based on the RISC-V instruction set, today announced that initial evaluations for its ET-SoC-1 AI inference accelerator are underway with lead customers. Additional slots are available to qualified customers who have an interest in AI inferencing accelerators for datacenter applications.

Esperanto Technologies is the AI RISC-V leader, offering massively parallel 64-bit RISC-V-based tensor compute cores currently delivered in the form of a single chip with 1088 ET-Minion compute cores and a shared high performance memory architecture. Designed to meet the performance, power and total cost of ownership (TCO) requirements of large-scale datacenter customers, Esperanto’s inference chip is a general purpose, parallel processing solution that can accelerate many parallelizable workloads. It is designed to run any machine learning (ML) workload well, and to excel at ML recommendation models, one of the most important types of AI workloads in many large datacenters.

https://www.hpcwire.com/off-the-wir...erencing-solution-now-in-initial-evaluations/

 

[Dark Kaeser]

MIPS Claims "Best-In-Class Performance" With New RISC-V eVocore CPUs

MIPS Tech is no longer working on their MIPS CPU instruction set architecture but has been taking on RISC-V based designs.

Today the company made the bold announcement for their new eVocore P8700 and I8500 multiprocessor IP cores that they offer "Best-In-Class Performance and Scalability."

With the new MIPS eVocore P8700 they are referring to it as offering "superscalar performance" and is said to be able to scale up to 64 clusters, 512 cores, and 1024 harts/threads. The eVocore P8700 is expected to be available in Q4.

The eVocore I8500 meanwhile is their efficiency offering that they says will be best-in-class power efficiency for SoC applications.

https://www.phoronix.com/scan.php?page=news_item&px=MIPS-New-RISC-V-May-2022

 

[Dark Kaeser]

https://twitter.com/i/web/status/1529030984045404161

 

[Dark Kaeser]

Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board

The Starfive VisionFive is a currently $179 USD RISC-V board that is intended to run full-blown RISC-V Linux distributions. The board comes in two varieties with 4GB or 8GB of system memory, powered by a dual-core SiFive U74 RV64 SoC @ 1.0GHz, NVDLA deep learning accelerator engine, Tensilica-VP6 Vision DSP, and a neural network engine. The board also has WiFi 802.11n, Bluetooth 4.2, HDMI output, four USB 3.0 ports, Gigabit Ethernet, and powered via USB-C or from the 40-pin GPIO header.

https://www.phoronix.com/scan.php?page=news_item&px=Ubuntu-VisionFive-WIP

 

[Dark Kaeser]

Untether.AI Boqueria 1458 RISC-V Core AI Accelerator​

Untether.AI has a common theme that data movement is expensive in terms of performance and power consumption. Part of the goal is to bring compute closer to memory to minimize movement.

Boqueria is a 2PF of FP8 processor built on TSMC 7nm. The 238MB of on-chip SRAM gives the chip around 1PB/s of SRAM bandwidth, plus it can access external memory. The FP8 is important as that is a key part of Boqueria’s architecture.

Each Memory Bank (the memory/ compute clusters on the NOC) has two multi-threaded RISC-V cores. All of these Memory Banks are connected via the NOC.

Here is a diagram of how Boqueria puts SRAM and compute together.

The RISC-V processor is a RV32EMC instruction set, but then custom instructions. That is part of the power of RISC-V.

Here is more detail about the on-chip NOCs.

The company says its architecture scales from very low power to higher power devices. It is not discussing 500W+ chips but is instead targeting M.2 type of power envelopes.

The idea is to then aggregate a number of these smaller chips to achieve more performance. Note that this will be a PCIe Gen5 device as well.

https://www.servethehome.com/untether-ai-boqueria-1458-risc-v-core-ai-accelerator-hc34/

O "interessante", além do uso dos custom "Risc-V" cores é afastar-se da tradicional "arquitectura PC", ali na 1ª imagem o modelo do lado esquerdo "Von Neumann", e colocar a memória e o "processador" juntos tudo interligado por rede (NoC - Network on Chip) se bem que estou na dúvida se isto é na topologia "Torus" ou "Mesh", dado que tem ali diferentes larguras de banda

The example of topologies in Network-on-Chip (NoC)​

isto para "retirarem" as limitações/custo das transferências de dados de/e para a memória.

Claro que isto é especialmente vantajoso para certos workloads intensivos e repetitivos como é o caso do AI, e obviamente SDK (Software) a acompanhar para se retirar essa vantagem.

 

[Nemesis11]

Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board

Foi anunciado o sucessor desse SBC.

• SoC – StarFive JH7110 quad-core 64-bit RISC-V (SiFive U74 – RV64GC) processor @ up to 1.5 GHz with
  • Imagination BXE-4-32 GPU supporting OpenGL ES 3.2, OpenCL 1.2, Vulkan 1.2
  • 4Kp30 H.265/H.264 video decoder
  • 1080p30 H.265 video encoder
• System Memory – 2GB, 4GB, or 8GB LPDDR4
• Storage – MicroSD card slot, eMMC flash module socket, M.2 M-Key socket for NVMe SSD, QSPI flash for U-boot
• Video Output
  • HDMI 2.0 port somehow limited up to 4Kp30
  • 4-lane MIPI DSI connector up to 2Kp30
  • 2-lane MIPI DSI connector
• Camera I/F – 2-lane MIPI CSI camera connector up to 4Kp30
• Audio – 3.5mm audio jack
• Networking – 2x Gigabit Ethernet RJ45 ports
• USB – 2x USB 3.0 ports, 2x USB 2.0 ports
• Expansion – 40-pin GPIO color-coded header
• Misc – Reset button, fan header, debug header
• Power Supply
  • Via USB-C port with PD support up to 30W
  • 5V DC via GPIO header (3A+ required)
  • PoE via additional module
  • On-board PMIC
• Dimensions – 100 x 72 mm (Pico-ITX form factor)

Benchmarks:

O SOC:

• CPU – Quad-core SiFive U74 64-bit RISC-V processor @ 1.8 GHz delivering 2.5 DMIPS/MHz
• Cache – 32KB I-cache, 32KB D-cache, 2MB level 2 cache
• GPU – “High-performance graphics processor” @ 850 MHz
• DSP – Dedicated vision DSP, audio DSP
• NPU – Independent AI engine delivering up to 4 TOPS @ 1.4 GHz
• VPU – 4Kp60 H.264/H.265 Video encoding and decoding, JPEG image codec
• System Memory – Up to 2x 32MBit LPDDR4/LPDDR4x, up to 4x 16Mbit DDR4 @ 4266 MHz
• Storage – eMMC 5.1, QSPI NOR flash, 2x SD4.0 UHS-I interfaces
• Video Output
  • 4-lane MIPI DSI 2.0
  • 2x LVDS interfaces
• Audio I/F – 4x I2S, 2x PDM, 1x Audio DAC
• Networking – 2x Gigabit Ethernet interfaces
• USB – 1x USB 3.2 Gen 1 Host, 2x USB 2.0 Host, 1x USB 2.0 OTG
• Other peripherals
  • 4x 12-bit SAR ADC
  • 4x I2C, 4x SPI, 6x PWM, 7x UART, GPIO
• Security
  • SiFive Shield
  • Safe boot
  • Hardware encryption engine, Hardware encryption engine
• Process – 12nm

https://www.cnx-software.com/2022/08/23/starfive-visionfive-2-quad-core-risc-v-sbc-linux/
https://www.cnx-software.com/2022/0...-risc-v-processor-comes-with-gpu-npu-and-dsp/

Parece ser bastante interessante.

 

[Dark Kaeser]

Yep, já tinha visto, o GPU da 1ª board já é baseado nos Imagination B series.

O 2° artigo (board da LeapFive) entretanto já foi feito um update, a confirmar o SoC, que assim sendo será baseado no mesmo Imagination B series, estou a estranhar é a diferença de velocidade do GPU de um SoC para o outro (up to 1.5Ghz e up to 800MHz).

 

[Dark Kaeser]

Aparentemente a Pine64 já está em produção

Pine64 Star64 SBC to feature StarFive JH7110 quad-core RISC-V processor with Imagination GPU​

Star64 preliminary specifications:

• SoC – StarFive JH7110 quad-core 64-bit RISC-V (SiFive U74 – RV64GC) processor @ up to 1.5 GHz with
  • Imagination BXE-4-32 GPU supporting OpenGL ES 3.2, OpenCL 1.2, Vulkan 1.2
  • 4Kp30 H.265/H.264 video decoder
  • 1080p30 H.265 video encoder
• System Memory – 4GB or 8GB LPDDR4
• Storage – MicroSD card slot, eMMC flash module socket, QSPI flash
• Video Output
  • HDMI 2.0 port
  • 4-lane MIPI DSI connector + touch panel connector
• Camera I/F – 2-lane MIPI CSI camera connector up to 4Kp30
• Audio – 3.5mm audio jack
• Networking
  • 2x Gigabit Ethernet RJ45 ports
  • On-board RTL8852BU WiFi 6 and Bluetooth 5.2 module and 2x u.FL antenna connectors
• USB – 1x USB 3.0 port, 3x USB 2.0 Type-A ports, 2x USB 2.0 interfaces via headers
• Expansion
  • 40-pin color-coded GPIO header
  • PCIe x4 slot
• Misc – Power button, fan header, 3-pin UART/debug header, DIP switch for boot configuration (flash, SD, eMMC, UART)
• Power Supply – 12V DC via power barrel jack or 4-pin header; on-board PMIC
• Dimensions – 133 x 80 mm

https://www.cnx-software.com/2022/0...0-quad-core-risc-v-processor-imagination-gpu/


usa o mesmo StarFive JH7110 de outra boards

StarFive JH7110 RISC-V processor specifications released​

Some documentation for the StarFive JH7100 processor has been released and answers some of those questions. It’s actually an SoC with six RISC-V cores, of which four 64-bit RISC-V cores run the main OS, plus a 64-bit RISC-V monitoring core, and a 32-bit RISC-V real-time core. The AI accelerators found in the JH7100 (Neural Network Engine and NVDLA) appear to be gone for good, and there are two 1-lane PCIe 2.0 interfaces up to 5 Gbps each.

StarFive JH7110 specifications:

• CPU sub-system
  • Quad-core 64-bit RISC-V SiFive U74 (RV64GC) processor @ up to 1.5 GHz with 32KB D-Cache, 32KB I-cache
  • Single-core 64-bit RISC-V SiFive S7 (RV64IMAC) monitor core with 16KB I-cache, 8KB DTIM
  • Single-core 32-bit RISC-V SiFive E24 (RV32IMFC) real-time control core with 16KB I-cache
  • Up to 2MB L2 cache
• GPU – Imagination BXE-4-32 GPU with support for OpenCL 1.2, OpenGL ES 3.2, Vulkan 1.2
• Video Decoder – H.265, H.264 4K @ 60fps or 1080p @ 30fps, MJPEG
• Video Encoder – H.265/HEVC Encoder, 1080p @ 30fps
• Memory
  • BUS RAM up to 256KB
  • Up to 8GB DDR4/3, LPDDR4/3 at 2133/2800 Mbps
• Storage
  • 2x SDIO/eMMC 5.0 host controllers
  • QSPI controller for up to 16MB SPI flash, up to 2GB SPI NAND flash
• Display interfaces
  • 1x HDMI 2.0 up to 4Kp60
  • RGB656, RGB888 up to 1080p30
  • MIPI DSI up to 2.5 Gbps or 1080p30
  • 1x DPI (Parallel RGB Display)
• Camera interfaces
  • 1x MIPI CSI-2 interface up to 6 lanes of 1.5 Gbps; support for 1x 4D1C or 2x 2D1C MIPI sensors up to 4Kp30
  • 1x DVP sensor input interface
• Audio
  • 32-bit audio DSP used for traditional audio/voice data algorithm processing
  • 8-channel TX and RX I2S/PCM TDM
  • 4x sets of I2S/PCM I/F with DMA support
  • 2x sets of SPDIF I/F, RX and TX modes
  • 4-channel PDM input for digital MIC
  • DAC output with PWM interface
• Networking – 2x Gigabit Ethernet with RMII/RGMII
• USB – USB 3.0 host/device (multiple with one PCIe interface), USB 2.0 host/device
• PCIe – 2x PCIe 2.0 x1 up to 5 Gbps per lane (Note one of the PCIe 2.0 interface is multiplexed with USB 3.0)
• Other peripherals
  • 6x UART, 7x I2C, 7x SPI
  • 2x CAN 2.0B Bus up to 1 Mbps
  • 7x 32-bit timers, 1x 32-bit WDT reset output
  • 1x temperature sensor
  • 3x GPCLK outputs
  • 2x INTC
  • 8x PWM outputs
  • 64x GPIO
• Security
  • Encryption: AES; DES/3DES; HASH; PKA
  • Compliant with TRNG
  • 256-bit random number generation
  • 512 x 32-bit (2 KB) of OTP for key data on-die storage
• Clock sources
  • 24 MHz for USB, GMAC, and system main clock source
  • 32.768 kHz for RTC clock source
• Voltages
  • 0.9V core voltage
  • 1.8V/2.5V/3.3V I/O voltage
• Boot modes
  • Boot Rom
  • QSPI NOR/NAND Flash
  • SD card/eMMC
  • UART/USB/SD card update
• Package – 17 x 17 mm, 0.65 mm ball pitch, FCBGA package with 625 balls

https://www.cnx-software.com/2022/08/29/starfive-jh7110-risc-v-processor-specifications/

 

[Nemesis11]

A Intel a puxar por Risc-V, até com uma board com FPGA para dev.

 

[Dark Kaeser]

NASA Selects SiFive’s RISC-V IP to Power Future Space Missions​

SiFive, Inc., the founder and leader of RISC-V computing, today announced it has been selected by NASA to provide the core CPU for NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor. HPSC is expected to be used in virtually every future space mission, from planetary exploration to lunar and Mars surface missions.

HPSC will utilize an 8-core, SiFive® Intelligence™ X280 RISC-V vector core, as well as four additional SiFive RISC-V cores, to deliver 100x the computational capability of today’s space computers. This massive increase in computing performance will help usher in new possibilities for a variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, communications, and other applications.

https://www.sifive.com/press/nasa-selects-sifive-and-makes-risc-v-the-go-to-ecosystem

 

[Dark Kaeser]

https://twitter.com/i/web/status/1569161878244564992

 

[Dark Kaeser]

SiFive Powers Google TPU, NASA, Tenstorrent, Renesas, Microchip, And More​

Many dismiss RISC-V for its lack of software ecosystem as a significant roadblock for datacenter and client adoption, but RISC-V is quickly becoming the standard everywhere that isn’t exposed to the OS. For example, Apple’s A15 has more than a dozen Arm-based CPU cores distributed across the die for various non-user-facing functions. SemiAnalysis can confirm that these cores are actively being converted to RISC-V in future generations of hardware.

SiFive has a variety of core IPs, with their E, S, and U series cores having varying levels of success. Despite their deceptive marketing, the P series is not that successful on its high-end P series cores. Today we want to talk about the X280 core, which has rapidly racked up wins. While us nerds are a bit partial to the next generation NASA High-Performance Space Flight CPU, the most significant win is with Google. SiFive announced a collaboration with Google on the TPU here at the AI HW Summit.

The core has relatively high performance despite being in order. The vector pipeline is very wide and implements the full RISC-V Vector 1.0 spec. Furthermore, it has extensions that support bfloat, matrix multiplies, and quantization, allowing it to be optimized for AI. This CPU is performant enough to run as an applications processor in automotive applications or a hypervisor in datacenter applications. Every one of Tenstorrent’s TenSix processor tiles includes X280 CPUs. There is even an automotive version with ISO certifications that can run in lockstep mode, which we believe will be deployed in Toyota cars.

SiFive can offer something Arm cannot, flexibility. Customers can modify their cores by adding hardware accelerators directly into the vector register file. This can be used for extending the X280 core to applications such as DSP, image signal processing, and AI. This is where the Google collaboration comes in.

Google already uses 3rd party ASIC design services with Broadcom for the TPU and VCU. The internal teams focus on what is differentiated to their use case. In the case of the TPU, it is the Matrix Multiply Unit and the Inter-Chip Interconnect. Google is taking a sensible approach to their TPUs by outsourcing redundant work. Instead of building everything from scratch, they will now use X280’s VCIX mode.

Google will utilize the base scalar and vector of X280 in a way that allows push/pop vector instructions. This richer set will enable functions to be overlayed. The programmability is much better as it can now execute python and run conditional routing more easily. Google retains the performance of the MXU but the programmability and well-understood CPU programming model that a RISC-V core offers. The MXUs have a high latency of ~100 cycles, while the CPU can execute scalar and vector code in a few cycles concurrently.

We had the chance to ask Google why they wanted to stick a CPU as part of every one of their accelerator units. This has a significant area impact of around 0.5mm2 per CPU core. Their MMX unit is around 1mm2 per unit, meaning a 50% overhead. The answer was well reasoned and primarily focused on programmability and flexibility.

We could have had a horrible one-off sequencer instead, but do you like to program your machines with low-level assembly?
Cliff Young, Google TPU Architect; MLPerf co-founder

https://semianalysis.substack.com/p/sifive-powers-google-tpu-nasa-tenstorrent

 

[Dark Kaeser]

https://twitter.com/i/web/status/1574945058901692416

 

[Dark Kaeser]

Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process​

Horse Creek is a Raspberry Pi-inspired RISC-V software development board. It’s physically quite a bit larger due to a large number of integrated interfaces. For example, there’s 8 GiB of DDR5. PCIe 5.0 slot. SPI Flash contains the U-Boot, and a myriad of other monitoring and debugging interfaces.

Within 18 months, Horse Creek went from an announcement to a fully working A0 stepping chip running Linux. Manufactured on the company’s most advanced Intel 4 process, the die measures just 4 mm by 4 mm and is packaged in a 19 mm x 19 mm BGA package.

The SoC itself integrates quad-core SiFive P550 RISC-V cores. Each core features private L1 and L2 caches with a shared last-level cache – all operating at 2.2 GHz. At the time of tape out those were the highest-performance RISC-V cores. Note that since SiFive actually announced next-generation P650 cores, surpassing them in performance. The SoC integrates Intel’s own PCIe 5.0 PHY with x8 lanes along with Synopsys PCIe 5 Controller. It also integrates Intel’s DDR5 PHYs supporting 5600 MT/s rates along with Cadence’s memory controller. Other Intel’s own Intel 4 IPs include 2 MiB of shared SRAM (part of their memory compiler), process monitor, caches, Power/Clock/PLLs, electronic fuses, JTAG, and various cell libraries.

https://fuse.wikichip.org/news/7277...-horse-creek-dev-platform-on-intel-4-process/

 

[Nemesis11]

SiFive Powers Google TPU, NASA, Tenstorrent, Renesas, Microchip, And More

Só agora estava a ler esse artigo e algo saltou-me à vista, que se calhar passou muito despercebido.

For example, Apple’s A15 has more than a dozen Arm-based CPU cores distributed across the die for various non-user-facing functions. SemiAnalysis can confirm that these cores are actively being converted to RISC-V in future generations of hardware.

Muito interessante. Não significa que a Apple, no futuro irá migrar para Risc-V, até porque isto são apenas pequenos microcontroladores que o utilizador final não tem visibilidade, mas é uma decisão importante.
De referir que a nVidia já fez esta migração há bastante tempo (Pascal?). Não foi de ARM, mas há algumas gerações que os GPUs da nVidia têm vários Cores Risc-V, para management interno.

Intel, SiFive Demo High-Performance RISC-V Horse Creek Dev Platform On Intel 4 Process

Volto a referir. Grande parte do mercado pensa que a Intel só existe, existindo x86 e acho que pelo historial da Intel e pelo seu CEO actual, isso é falso.
Também acho que a Intel irá usar Risc-V como "cavalo de troia" contra a ARM.

 

[JAFoNEXUS]

Também acho que a Intel irá usar Risc-V como "cavalo de troia" contra a ARM.

Sim, tb me parece precisamente isso.
Como deixaram para trás a ARM há mtos anos, têm todo interesse em apostar nesta arquitectura.

Têm todo o interesse q a ARM perca o folego q tem actualmente (mobile, server e Apple) !