Processador Risc-V


Jim Keller on AI, RISC-V, Tenstorrent’s Move to Edge IP​

“My belief is in the next 5 to 10 years, RISC-V will take over all the data centers,” Keller told EE Times, adding that this is especially true for scientific computing and HPC. He said supercomputing could dominate even faster.
In a surprise move for a data center chip company, Tenstorrent recently licensed both its Tensix AI accelerator core IP and its Ascalon CPU core IP to LG Electronics. The Korean consumer electronics giant plans to use the Tensix IP at the embedded edge, in smart TVs and automotive chips. The two companies also plan to collaborate on future generations of RISC-V CPU, AI accelerator and video codec IP and/or chiplets. (LG spun out its own AI IP division in 2020).


Esperanto Merging HPC and ML in Upcoming RISC-V Processor​

Esperanto Technologies has ambitious plans for its next RISC-V processor: to undo the accelerator model and build a chip that has both CPU and GPU capabilities for machine learning and high-performance computing.
Ditzel also shared some details about its next-generation chip that he hopes would serve that purpose: do double-precision computing for HPC, and lower-precision computations for machine learning applications.

The ET-SoC-2 will include new high-performance CPU cores with the RISC-V vector extensions. The RISC-V standards-setting organization, RISC-V International, is in the process of ratifying new vector and floating-point specifications to be included in the base instructions. The full list is available here.

Esperanto’s focus is more on power efficiency than raw performance, which has been Ditzel’s focus for decades. In 1995, he co-founded Transmeta, which had a software-defined chip that emulated x86 processors and was focused on power efficiency.

Unleashing An Open Source Torrent On CPUs And AI Engines​

In January of this year, Keller was tapped to replace Bajic as chief executive officer, and the company is today announcing that it will bring in somewhere between $120 million and $150 million in its Series D funding, with Hyundai Motor Group and Samsung Catalyst Fund leading the round and with prior investors Fidelity Ventures, Eclipse Ventures, Epiq Capital, Maverick Capital, and others kicking in dough. To date, that will being the investment kitty to somewhere north of $384.5 million and will probably boost its valuation above $1.4 billion.

All that money is interesting, and necessary to pay for the substantial amount of engineering work that the Tenstorrent team needs to do to create a line of commercial-grade RISC-V server processors and AI accelerators to match them and, more importantly, to take on the hegemony of the Nvidia GPU in AI training. It is going to take money – and maybe a lot more money, and maybe not – to help companies cut the costs of AI training. What we do know is that Keller thinks he has just the team to do it, and we had a chat with him about the Tenstorrent mission, one that we have been looking forward to.

TPM: Yeah, but we got we have got so many different companies already in the game. None of it has worked to my satisfaction. It’s not like the Groq guys took the TPU idea, commercialized it, we’re done. It’s not like MapReduce and Yahoo Hadoop. Nirvana Systems and Habana Labs both had what I think were good architectures, and Intel has not had huge success with either. Graphcore and SambaNova are reasonable, Cerebras has waferscale and that is interesting. Esperanto is in there, too, with RISC-V. And everybody, as far as I can see, has a billion dollar problem to get to the next level. I know RISC-V is important, that it is the Linux of hardware and we’ve been waiting a long time for that moment. Using RISC-V to build an accelerator is the easy part of making an architectural choice.

What is it that Tenstorrent is doing can do that is different, better? I don’t expect you to spill all the architectural beans today, but what is driving you, and why?
Jim Keller:...
I don’t think GPUs are the be all and end all of how to run AI programs. Everybody who describes an AI program, they describe a graph, and the graph needs to be lowered with interesting software transformations and map that to the hardware. That turns out to be a lot harder than is obvious for a bunch of reasons. But we feel like we’re actually making real progress on that. So we can make an AI computer that’s performant, and that works well and is scalable. We’re getting there.

The other is thing is that we started building a RISC-V – and we at Tenstorrernt we had long chats about this – and we think the future is going to be mostly AI. There is going to be interaction between general purpose CPUs and AI processors, and that program and software stack, and they are going to be on the same chip. And then there’s going to be lots of innovation in that space. And I called my good friends at Arm and said that we want to license it and it was a too expensive and they didn’t want to modify it. So we decided to build our own RISC-V processor. And we raised money partly on the last round on that thesis that RISC-V is interesting.

TPM: That was my next question. If you look at companies like Cerebras and SambaNova, they are really becoming cloud vendors or suppliers to specific cloud vendors looking for a niche and also a way to get AI done cheaper and easier than with GPUs from Nvidia. By my math, it looks like you need around $1 billion to train a next-gen AI model, and that money has to come from somewhere, or a way has to be found to do it cheaper.
Jim Keller: ...

We’re on the journey. I told somebody recently, when things don’t work, you have a science project; when things work, you have a spreadsheet problem. A spreadsheet is like this. Our current chips are in Globalfoundries 12 nanometer. And somebody says, how fast would it be if you ported it to 3 nanometers. There’s no rocket science to it. You know performance of GF12 and TSMC 5N, 5N, and 3N, and you just spreadsheet it out and then ask, “Is that a compelling product?”
Última edição:
Iria acontecer mais cedo ou mais tarde

Leading Semiconductor Industry Players Join Forces to Accelerate RISC-V

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor, NXP Semiconductors, and Qualcomm Technologies, Inc., have come together to jointly invest in a company aimed at advancing the adoption of RISC-V globally by enabling next-generation hardware development.
Formed in Germany, this company will aim to accelerate the commercialization of future products based on the open-source RISC-V architecture. The company will be a single source to enable compatible RISC-V based products, provide reference architectures, and help establish solutions widely used in the industry. Initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.
Interessante ser uma Joint Venture e não algo in house de uma Qualcomm ou uma NXP. Parece-me que também servirá para testar as águas.
Bom todas elas já fazem parte da RISC-V Foundation.

Tendo em conta que estão aí não só as 3 maiores empresas de semicondutores europeias mas também simultaneamente 3 das maiores do mercado embedded (ficou a faltar a TI e a ST-Micro) - apesar de a Bosch nunca aparecer nestas tabelas


o objectivo será os microcontroladores (ARM Cortex Mx) e depois partir daí.

Da lista acima a Renesas já tinha licenciado o RISC-V à empresa de IP, Andes Technology, e já produz produtos para vários mercados incluindo o industrial e automóvel.
Este anuncio terá alguma relação com aquela Joint Venture?

TSMC, Bosch, Infineon, and NXP Establish Joint Venture to Bring Advanced Semiconductor Manufacturing to Europe​

Hsinchu, Stuttgart, Munich, Eindhoven, Aug 8, 2023 – TSMC (TWSE: 2330, NYSE: TSM), Robert Bosch GmbH, Infineon Technologies AG (FSE: IFX / OTCQX: IFNNY), and NXP Semiconductors N.V. (NASDAQ: NXPI) today announced a plan to jointly invest in European Semiconductor Manufacturing Company (ESMC) GmbH, in Dresden, Germany to provide advanced semiconductor manufacturing services. ESMC marks a significant step towards construction of a 300mm fab to support the future capacity needs of the fast-growing automotive and industrial sectors, with the final investment decision pending confirmation of the level of public funding for this project. The project is planned under the framework of the European Chips Act.

The planned fab is expected to have a monthly production capacity of 40,000 300mm (12-inch) wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology, further strengthening Europe’s semiconductor manufacturing ecosystem with advanced FinFET transistor technology and creating about 2,000 direct high-tech professional jobs. ESMC aims to begin construction of the fab in the second half of 2024 with production targeted to begin by the end of 2027.

The planned joint venture will be 70% owned by TSMC, with Bosch, Infineon, and NXP each holding 10% equity stake, subject to regulatory approvals and other conditions. Total investments are expected to exceed 10 billion euros consisting of equity injection, debt borrowing, and strong support from the European Union and German government. The fab will be operated by TSMC.

Não é referido Risc-V, até porque não faria sentido construir uma fábrica só para chips com uma ISA, mas 3 das empresas são as mesmas, aqueles processos de fabrico, em 2027, serão muito maduros e o investimento também é na Alemanha.
Isto é, parece-me que esta fabrica poderá ser o lado a nível de fabrico daquela Joint Venture.
Coloquei essa notícia no tópico da "Escassez mundial de IC", e para já não me parece relacionado, dado que essa notícia fala especificamente do mercado auto

Dr. Stefan Hartung, chairman of the Bosch board of management: “Semiconductors are not only a crucial success factor for Bosch. Their reliable availability is also of great importance for the success of the global automotive industry. Apart from continuously expanding our own manufacturing facilities, we further secure our supply chains as an automotive supplier through close cooperation with our partners.
Jochen Hanebeck, CEO of Infineon Technologies. “Infineon will use the new capacity to serve the growing demand particularly of its European customers, especially in automotive and IoT. The advanced capabilities will provide a basis for developing innovative technologies, products and solutions to address the global challenges of decarbonization and digitalisation.”
Kurt Sievers, President and CEO of NXP Semiconductors. “We thank the European Union, Germany, and the Free State of Saxony for their recognition of the semiconductor industry’s critical role and for their true commitment to boost Europe’s chip ecosystem. The construction of this new and significant semiconductor foundry will add much needed innovation and capacity for the range of silicon required to supply the sharply increasing digitalization and electrification of the automotive and industrial sectors.”

e será para garantirem a produção dos seus chips integrados mais avançados para ADAS/condução autónoma, mas esses à partida devem usar core ARM, não estou a ver usarem RISC-V em 3 anos, sem recorrerem a 3os.
Finalmente uma noticia realmente importante. :D Um Jogo x86 que usa OpenGL, a correr num SOC Risc-V. :)

O suporte está na ultima versão do emulador Box64. :) No exemplo no vídeo também é usado o gl4es.
Box64 Dynarec now support RISC-V! Thanks to github user ksco and xctan for their huge code contribution on the RV64 Dynarec, joined by wannacu at the end, the Dynarec is now complete for most usuals opcodes, and many x87 and SSE/SSE2 opcodes too. While not as efficient as the ARM64 one, it’s still a nice speed up and allow game to be played, like Stardew Valley on a Star Five 2 sbc (also using gl4es for the OpenGL driver, that’s a lot of emulation and translation layer here!)

Aquele jogo está a ser executado com um binário nativo Linux x86, mas se o Wine também estiver a funcionar como no Box64 em ARM, será possível correr jogos Windows x86.
Milk-V Launches Milk-V Vega, the World’s First RISC-V Open Source 10 Gigabit Ethernet Switch

On August 19, 2023, Shenzhen MilkV Technology Co., Ltd (Milk-V) unveiled the world’s first RISC-V open-source 10-gigabit Ethernet switch - the Milk-V Vega. The core control chip utilizes the FSL1030M network switch chip developed by Wuhan Binary Semiconductor Corporation.
The FSL91030M integrates 8 ports of gigabit Ethernet PHY, supporting 10/100/1000BASE-T and 100BASE-FX functionalities. It also incorporates 2 ports of 10G SerDes, enabling support for 1000BASE-X, SGMII, QSGMII, O-USGMII, and 10G BASE-R functionalities. Additionally, it includes 4 ports of 1G SerDes, capable of supporting 1000BASE-X and SGMII functionalities. The combination of 4 ports of 1G SerDes and 4 ports of gigabit Ethernet PHY can be configured as 4 Combo ports. The FSL91030M further supports 2 ports of RGMII/GMII/MII interfaces, serving as expandable management interfaces.

The FSL91030M is built upon Nuclei System Technology Co., Ltd.'s UX608 uCore architecture. It supports the RV32/64 IMACFDPB instruction set and adopts a 6-stage variable-length pipeline architecture to achieve high frequency and performance, meeting the demands of high-performance embedded scenarios. This core supports configurable dual-mode capabilities, allowing for switching between real-time processors and application processors. It also provides a 64-bit AXI system bus interface, AHB-Lite private peripheral interfaces, ILM/DLM interfaces, and slave interfaces.

Ventana Veyron V1 RISC-V Data Center Processor Hot Chips 2023​

At Hot Chips 2023, Ventana Micro a RISC-V CPU startup showed off its new data center Veyron V1. The Ventana Veyron V1 looks to the new era of RISC-V CPUs for the data center. While this is on the V1 product, the company apparently already has V2 working.
The idea is that Ventana Micro has a RISC-V CPU core, up to 16 cores per chiplet, then combines them with an I/O hub that has things like DDR memory controllers and PCIe. Ventana says it can scale Veyron V1 up to 192 cores but it can also integrate domain-specific accelerators.

Here are the key specs including the cores, cache, and more on the chip. Ventana says that Veyron V1 will have support for things like virtualization as well as measures making it more resilient to side-channel attacks.


From a processor cluster size, each 16 core cluster has up to 48MB of L3 cache.


Ventana also has a reference Veyron V1 implementation that can be used for TSMC 5nm.
Outro artigo sobre esse Ventana:


V1 has a set of very unique design decisions. Deviating from the norm is risky because engineers have figured out what works and what doesn’t over the history of CPU design. That’s why successful CPUs share a lot of common design features. Ventana looks to have done a reasonably good job of making sure they didn’t fall into any obvious holes. They’ve mitigated VIVT cache shortcomings with hardware synonym handling and ASID filtering. Their split L2 design has enough caching capacity on both the instruction and data side. Their large, single level BTBs and TLBs either have low enough latency to not hold back performance, or are placed away from the most performance critical paths.

Even though Veyron V1 is a first generation design from Ventana, it’s likely a competent contender for scalar integer applications. Ventana will have a much harder time on throughput bound applications. V1 has no vector capability, and even if V2 does, the RISC-V ecosystem is even less mature than ARM’s. Software will have to be written to support RISC-V’s vector extensions. There’s a ton of throughput bound software out there, from video encoders to renderers to image processing applications. They’re maintained by a lot of different people with different priorities, so new instruction set extension support tends to move slowly. ARM already faces a software support struggle as it tries to establish itself as a viable alternative to x86, and RISC-V faces an even greater challenge in that area.

A SiFive também apresentou um novo Core, o P870.


This is a 32-core chip example with 8x 4-core clusters.

Here is a consumer topology with two P870 higher-performance cores, four P470’s, smaller more efficient cores in a cluster, and then a low-power E6 in-order core for always-on at low power.

This is not a product announcement. The product announcement will be in a few weeks apparently and the clock speeds are expected to be in the 3GHz range. This was cool to hear about. RISC-V has a lot of momentum and SiFive has been a big player. SiFive is almost starting to feel like it is trying to become the Arm of the RISC-V market but with RISC-V as an ecosystem being open.

Mais um Core que é agrupado em Clusters de 4 Cores cada, em que cada Cluster de 4 Cores partilha Cache L2 e a Cache L3 é distribuída.
Também é interessante, no exemplo de um Processador para o mercado Consumidor, além dos "Big" (P870) e "Little" (P470) Cores, inclui também 1 Core "Low Power in order" (E6) para estar "allways on". Acho que vamos ver algo semelhante, por parte da Intel, nos próximos tempos. :)
Última edição:
O projecto da UE, para supercomputadores, que inclui cores Risc-V foi apresentado. :)

Marenostrum Experimental Exascale Platform (MEEP):





The computational components will be organized into hierarchical layers by following a bottom-up approach, starting at module-level and building on top of that by composition, up to a system-level component. This one can be seen as the computational engine, which will be a RISC-V based accelerator.

The targeted accelerator in MEEP is called Accelerated Compute and Memory Engines (ACME)
Each VAS Accelerator Tile is designed as a multi-core RISC-V processor, capable of processing both scalar and vector instructions. Going down, each core is a composition of three elements: a scalar core and three coupled co-processors.
  • Scalar core: It is a traditional RISC-V scalar processor with the capability of recognizing coprocessor and special instructions, for it (RISC-V vector and systolic array extensions) and resend them to one of its co-processors.
  • Co-processors: These units are added to the accelerator design with the aim of accelerating as much as possible the computation and memory operations, but also reducing power consumption and data movements.
Era mais ou menos expectável

RISC-V Responds to U.S. Lawmakers: Open Standards Are Important​

RISC-V International, an organization overseeing development of the open source RISC-V instruction set architecture, this week responded to U.S. lawmakers, who last week expressed concerns that openness of the RISC-V technology could be abused by the Chinese Communist Party and expressed an idea to 'close' the ISA from Chinese entities. Calista Redmond, chief executive of RISC-V International, believes that the ISA must remain open to enable evolution of compute capabilities for a broad range of applications.

"RISC-V is here to stay. It has already grown tremendously in global adoption and influence as the open standard for compute," Redmond wrote in a blog post. "RISC-V is an open standard and has incorporated meaningful contributions from all over the world. As a global standard, RISC-V is not controlled by any single company or country."
E assim começa...

Qualcomm to Bring RISC-V Based Wearable Platform to Wear OS by Google​

  • Qualcomm and Google are extending theircollaboration on wearables by developing a RISC-V Snapdragon Wear™ platform thatwill power next-generation Wear OS solutions.
  • Work has begun and will continue, to ensurethat applications and a robust software ecosystem for RISC-V will be available forcommercial launches.
  • Qualcomm plans to commercialize the RISC-Vbased wearables solution globally including the U.S.
Ventana Veyron V1 RISC-V Data Center Processor Hot Chips 2023

Imagination and Ventana to develop RISC-V CPU-GPU​

Both companies will collaborate to create chiplet heterogeneous SoC.
To build such a heterogeneous SoC, Ventana turned to one of the most experienced GPU IP companies, Imagination Technologies. Both companies are premier members of RISC-V International and the RISC-V Software Ecosystem (RISE) project and are strong advocates of open architecture.

Though there are over 3,000 member companies involved with the software ecosystem development, this partnership between Ventana and Imagination is an important step forward for the industry, as it brings together two processor developers in their respective fields. With their combined expertise in CPUs and GPUs, the two companies are well positioned to bring a new configuration to the RISC-V open architecture.
Ventana is about to launch the Veyron V2 next week, so this launch is aligned around that.
The two companies will be showing an emulation model of an Imagination GPU working with a Ventana RISC-V CPU at the RISC-V Summit next week. Ventana is about to launch the Veyron V2 next week, so this launch is aligned around that. The key change with V2 is that the RISC-V ISA now has most of the necessary features to compete with x86/Arm such as a standard vector extension and IOMMU specification.

Slide interessante.

Já agora, na agenda da "RISC-V Summit", aparecem títulos de apresentações e nomes de empresas interessantes. Destaco especialmente os temas e participação das apresentações da Meta, Samsung e Microsoft.
Keynote: Building Data Center Scale SoC's using RISC-V at Meta - Prahlad Venkatapuram, Senior Director of Engineering, Meta

Keynote: Unlocking Innovation with RISC-V and Qualcomm - Ziad Asghar, Senior Vice President of Product Management, Qualcomm Technologies, Inc (QTI)

Preparing for a Valid Performance Evaluation of RISC-V AP, in the Mobile Space - Jamie Kim, Samsung Electronics

The RISC-V Zjid Extension - Derek Williams, IBM

Keynote: Red Hat and RISC-V: To the Far Edge and Beyond - Stephen Watt, Distinguished Engineer, Vice President, Office of the CTO, Red Hat

Demo: Catapult Studio for Imagination RISC-V CPUs - Simon Harvey, Imagination Technologies

Demo: NVIDIA's use of Catapult HLS for Building ML Inference Accelerators - Stuart Swan, Siemens

Finding Common Ground - the Boot and Runtime Services (BRS) Specification - Andrei Warkentin, Intel

Introduction to Project CHERIoT
- Kunyan Liu, Microsoft

Demo: The Future of Ubuntu on RISC-V - Gordan Markus, Canonical
Poderá ser uma das razões?

Trouble Brewing For RISC-V As Issue Of Technology Transfer Is Questioned​

Within the messy world of international politics, a major consideration by governments concerns which types of kn0w-how and technology can be transferred and sold to other nations, with each type facing restrictions depending on how friendly the political relations are with the target country at that point in time. Amidst all of this, there are signs that a so far relatively minor player in the world of CPU instruction set architectures – RISC-V – may become a victim of this, as a bipartisan group of US politicians is petitioning the White House to restrict transfer of know-how (so-called Intellectual Property, or IP) to RISC-V, as this may benefit adversaries like China.

As a US citizen who is involved in the RISC-V ecosystem, [Andrew ‘bunnie’ Huang] feels rather strongly about this, and has written an open letter to the US President, pleading to not restrict the way that US citizens can deal with the Switzerland-based RISC-V organization. This comes as the California-based RISC-V startup SiFive has announced that it’ll lay off 20% of its workforce. Depending on how a restriction on RISC-V is implemented, this could mean that US citizens would be forbidden from contributing to this ISA and surrounding ecosystem.

China has made it clear that RISC-V is a big part of its strategy to loosen its dependence on the West along with its investments in its MIPS-based Loongson processors, all of which strengthens the case for restricting US participation in RISC-V, even if it forces US companies like SiFive to move countries or cease its operations.

The Letter​

To President Biden and the White House staff:

Recently, a letter was sent to the White House and the Secretary of Commerce by 18 lawmakers asking how the US plans to prevent China “from achieving dominance in … RISC-V technology and leveraging that dominance at the expense of US national and economic security”.

I am a Michigan-born American with a PhD from MIT in electrical engineering. I’m also a small business owner who designs and manufactures electronics. I am writing to urge you to not place any restrictions on the sharing of RISC-V technology.

My products’ CPUs are based on the open source RISC-V standard. RISC-V’s openness specifically benefits small businesses such as mine. I get tools and designs from the open source community, and I contribute my improvements back to the pool. Barrier-free participation in this vibrant open source ecosystem keeps overhead low, allowing me to be competitive in the cutthroat hardware business.

Like the Internet, RISC-V is already a global phenomenon. There are already prolific contributions from the EU, India, China, and more [1]; the US is not the sole proprietor of RISC-V implementations. I use an implementation of RISC-V called the VexRiscv, which is developed in the EU. Any barrier for US persons’ participation will only slow American progress in developing and adopting this technology. It will have an effect opposite of that intended by lawmakers.

A further subtlety is that RISC-V is simply a standard. It defines a set of words used to tell a chip to do something, similar to how we rely on a dictionary to define the meaning of English words. Just as one can write secret documents using openly defined words, designs using the RISC-V standard can be proprietary, even if the standard is open. The benefits of open standards are so well established that the US has an entire agency – NIST – to promote American innovation and industrial competitiveness by publishing open standards.

Furthermore, it is not practical to police the use of an established standard: once a book is published, it is impractical to ensure that none of America’s enemies obtain a copy of it. This has long been a trade-off of American innovation philosophy: we can freely exercise our First Amendment rights to share ideas, creating a vibrant intellectual exchange, even at the risk of others benefiting from reading our textbooks, journals and patents.

I believe this trade-off has been in our favor. With every exchange – even with potential competitors – we learn more. Chilling our freedom of expression to achieve administrative outcomes is a page out of other more oppressive regimes’ playbooks: it is fundamentally un-American to restrict the flow of ideas.

In summary, any restrictions placed on US persons sharing RISC-V technology would only serve to diminish America’s role as a technological leader. Over-broad restrictions could deprive educators of a popular tool used to teach students about computers on American campuses, for fear of also accidentally teaching to an embargoed entity. And even narrow restrictions on RISC-V could deprive US tech companies with any potential exposure to the Chinese market of access to a cost-effective, high-performance CPU technology, forcing them to pay royalties to the incumbent near-monopoly provider, ARM Holdings plc – a company that isn’t American. This weakens American competitiveness and ultimately harms the US’s best interests.

If the administration agrees that RISC-V is a technology so critical to US economic and military interests that it deserves special attention, instead of trying to restrict its expression with a federally-mandated licensing regime, it should invest in programs to develop more home-grown American RISC-V chip maker success stories. It is already within the four corners of existing US legal framework, and the RISC-V contractual framework, for companies to choose to develop proprietary implementations of RISC-V CPUs. The US has strong precedents for companies navigating the boundaries of open standards and finding success without the need for federal guidance: Intel and AMD are American industrial juggernauts built around proprietary implementations of an otherwise openly documented “x86” computer standard. What the US needs is an American answer to ARM Holdings plc’s monopoly, and that answer comes from investing in US companies that embrace RISC-V.

President Biden, I urge you: have faith in American innovation. Have faith in American values. Do not place any restrictions on the sharing of RISC-V technology. We can work together to build more US chip maker success stories, while embracing the American value of freedom of expression!

Very truly yours,

Andrew ‘bunnie’ Huang
An American Hacker, Maker, and Author

Não é a primeira vez que os Estados Unidos colocam restrições, algumas das vezes a nível de exportações e, que me lembre, mais a nível de software que hardware.
Essas restrições ou tentativas, na prática, acho que foram pouco eficazes e colocaram mais o foco nesse assunto. Uma especie de "Streisand effect". Estou-me a recordar das limitações à exportação de criptografia ou do DeCSS.

Mas neste caso parece-me ainda pior. A consequência seria a auto-exclusão dos Estados Unidos de uma tecnologia, que pode vir a ter grande sucesso, com ou sem a participação de cidadãos de nacionalidade americana.
Caso isto vá para a frente, é um tiro nos pés.

Também me parece que é capaz de explicar, pelo menos em parte, os Layoffs na SiFive. :)