TSMC 5nm

[Dark Kaeser]

TSMC taped out its first chip in a process making limited use of extreme ultraviolet lithography and will start risk production in April on a 5-nm node with full EUV.

Its N5 that will use EUV on up to 14 layers will be ready for risk production in April. EUV aims to lower costs by reducing the number of masks required for leading-edge designs.

TSMC said that N5 will deliver 14.7% to 17.7% speed gains and 1.8 to 1.86 area shrinks based on tests with Arm A72 cores.

Chip designs for the N5 node can start today, although most EDA tools won’t hit a 0.9-version readiness until November. Many of TSMC’s foundation IP blocks are ready for N5, but some, including PCIe Gen 4 and USB 3.1, may not be ready until June.

One source pegged total costs for an N5 design including labor and licensing at $200 to $250 million, up from $150 million for a 7-nm chip today, limiting pursuit of Moore’s Law to the well-heeled.

https://www.eetimes.com/document.asp?doc_id=1333827&page_number=1

Há um erro no artigo: menciona os ganhos de até 17% speed gains e acaba a frase com «a TSMC não menciona speed gains»

EDIT: já não bebo mais nada hoje: "The N7+ node can deliver 6% to 12% less power and 20% better density; however, TSMC did not mention speed gains." a não menção aos speed gains referem-se aos 7nm+ e não aos 5nm
(acabei por apagar do quote para não criar confusão)

Seja como for, acho que o investimento da TSMC ascenderá aos 25$B, os preços para o desenvolvimento irão subir também, imagino que o preço das wafers também

Apesar de o PDK (process design kit) ainda estar na versão 0.9 e portanto ainda não finalizado, os EDA partners já anunciaram a disponibilização dos mesmos:

- Cadence
- Synopsis
- Mentor

 

[Dark Kaeser]

Tradução do artigo original, em chinês.

TSMC's 5nm breakthrough, 3 major customers (Apple, HiSilicon, AMD) fight for capacity

https://www.chinatimes.com/realtimenews/20191204000010-260410?chdtv

https://twitter.com/chiakokhua/status/1201939134928977920

 

[miguelbazil]

50% de yield ainda é considerado de risco, interessante. @Dark Kaeser quando é que deixa de ser de risco? Aos 80%?

EDIT: fui investigar, risk production é apenas a primeira produção de algo em que tudo deve funcionar, mas que ainda não houve uma produção final anterior.

Essencialmente, é a primeira produção em larga escala, em que tanto o produtor, como o cliente, estão a correr um risco pois não sabem ainda se vai funcionar tudo bem no produto final, e com que yields.

 

[Rafx]

50% de yield ainda é considerado de risco, interessante.

E ainda assim é yield melhor do que Intel conseguiu nos 10 nm, após anos e anos, e milhares de milhões de investimento, e até ter voltado atrás e reformulado os 10nm..


(Isso pelo menos até á pouco tempo atrás)

 

[Dark Kaeser]

@miguelbazil já chegaste à conclusão por ti.

Basicamente há 3 etapas:
1. Tape out - quando o desenho do chip está finalizado e é feita a mask para usar na "impressão" da wafer;
2- Risk production - algumas wafers com o desenho final, serve para começar a preparar o lançamento propriamente dito (desenvolver firmware, drivers, BIOS e por aí fora)
3 - HVM - que traduzido significa High Volume Manufacturing, que se explica a si mesma.

Tudo isto pode demorar quase 1 ano ou mais.

Tudo começa no desenvolvimento do processo propriamente dito, em que a foundry por regra usa um chip padrão para poder comparar os processos entre si.
Começa então a ser preparado o chamado PDK (Process design Kit) que incluí as informações necessárias para os chamados EDA developers, (que no 1º post anunciam a disponibilização das mesmas integradas nas suas próprias ferramentas), e que regra geral incluí não só o SW mas também hardware para a emulação, normalmente baseado em FPGA.
https://www.cadence.com/en_US/home/...otium-s1-fpga-based-prototyping-platform.html
https://www.synopsys.com/implementation-and-signoff/fpga-based-design/fpga-based-prototyping.html
https://www.mentor.com/products/fv/questa/

Isto é o que ocupa boa parte do tempo de desenvolvimento de "chips", testar e simular tudo em ferramentas, até à hora da verdade com o tape out, que é suposto validar o trabalho feito... ou não. Notar que nem sempre os chips são desenvolvidos com o processo finalizado, ás vezes os chips podem começar a ser desenvolvidos com PDK 0.5 e quando o processo se aproxima da versão final 1.0 pode ter havido mudanças que podem gorar parte da permissa original do chip. (Ex um chip desenvolvido para altos clocks e depois no final o processo não permitir atingir esses clocks ou exigir demasiada voltagem).

Mas ultimamente tem-se apostado na cloud, ainda há tempos tinha postado no tópico das Vega II 7nm, para a verificação do "desenho" final

AMD engineers executed a physical verification pass of the Radeon Instinct™ Vega20 -- its largest 7nm chip design -- in ~10 hours using the TSMC-certified Calibre™ nmDRC software platform from Mentor, a Siemens business, running on the Microsoft Azure cloud platform using HB-series virtual machines, powered by AMD EPYC™ processors.

Using TSMC 7nm Calibre design kits running in Azure, AMD successfully completed two verification passes in ~19 hours – a dramatic reduction in total physical verification turnaround time, despite the massive 13.2B transistors on the AMD design. In addition, AMD scaled Calibre nmDRC out to 4,140 cores across 69 HB virtual machines, enabling its engineers to balance tight deadlines against demanding resource requirements and other costs

https://semiwiki.com/forum/index.ph...stem-partners-microsoft-azure-and-tsmc.11599/

 

[Rafx]

Update do Ian

Portanto a questão dos 50% de yields não é bem assim.
Claro que mesmo assim os yields podem já ser comparáveis/superiores aos yields dos 10nm da Intel..

Em breve devemos saber como estão os 5nm da TSMC.

 

[Nemesis11]

O artigo do Anando. Li na diagonal, mas se bem percebi, nos primeiros testes a 5 nm, com uma die de 17.92 mm^2, com 256 Mbits de SRAM e alguma lógica, têm uma média de 80% de yelds e o máximo de >90% de yelds.

Extrapolando para um die size de 100 mm^2, teria um yeld de +/- 32%.

O artigo tem mais informação.

https://www.anandtech.com/show/15219/early-tsmc-5nm-test-chip-yields-80-hvm-coming-in-h1-2020

 

[Dark Kaeser]

IEDM 2019 – TSMC 5nm Process

TSMC’s disclosures
The key bullet points from the TSMC paper and presentation are:

• Industry leading 5nm process.
• Full fledged EUV, >10 EUV layers replacing >3 immersion layers each resulting in a reduction in mask count improving cycle time and yield. The paper says >4 immersion layers for each EUV layer but in the presentation the presenter said >3.
• High mobility channel FETs.
• 021µm2 high density SRAM.
• ~1.84x logic density improvement, ~1.35x SRAM density improvement and ~1.3x analog density improvement.
• Gate contact over diffusion, unique diffusion termination, EUV based gate patterning for logic and SRAM.
• ~15% speed gain or 30% power reduction.
• Low resistance and capacitance interconnect with enhanced barrier lines and etch stop layer (ESL) with copper reflow gap fill. The Back-End-Of-Line (BEOL) also features a high resistance resistor for analog use and super high-density Metal-Insulator-Metal (MIM) capacitors
• 5 and 1.2 volt I/O transistors.
• True multi-threshold voltage process with 7 threshold voltages over a >250mv range supported and an extreme low Vt transistor 25% faster than the previous generation. Presumably only around 4Vts are available at a time.
• Passed qualification.
• High yielding test chip with 256Mb SRAM and CPU/GPU/SOC blocks and D0 ahead of plan with a faster yield ramp than any previous process. 512Mb SRAM has ~80% average yield and >90% peak yield.
• In risk production now with 1st half 2020 planned high volume production.

https://semiwiki.com/semiconductor-manufacturers/intel/280519-iedm-2019-tsmc-5nm-process/

 

[Dark Kaeser]

foto de uma Mask do AMD Thoroughbred A numa wafer de 8" (200mm)

A slightly different kind of mask/stencil for an 8" AMD Thoroughbred(A) wafer

https://twitter.com/david_schor/status/1206981410998956032

 

[Dark Kaeser]

TSMC Unveils Details of 5nm CMOS Production Technology Platform Featuring EUV and High Mobility Channel FinFETs at IEDM2019

Back in April, 2019, TSMC announced that they were introducing their 5 nm technology in risk production and now at IEDM 2019 they brought forth a detailed description of the process which has passed 1000 hour HTOL and will be in high volume production in 1H 2020. This 5nm technology is a full node scaling from 7nm using smart scaling of major design rules (gate, fin and Mx/Vx pitches) for improved yield featuring an SRAM cell of 0.021um2 and a declining defect density D0 that is ahead of plan.

A primary reason for the success of the 5nm technology platform is the implementation of Extreme Ultra-Violet (EUV) photolithography. Fully-fledged EUV replaces at least four times more immersion layers at cut, contact, via and metal line masking steps for faster cycle time, better reliability and yield. Total mask count in 5nm is several masks less than in the previous 7nm node.

https://semiwiki.com/semiconductor-...nd-high-mobility-channel-finfets-at-iedm2019/

 

[Nemesis11]

TSMC Announces 2x Reticle CoWoS For Next-Gen 5nm HPC Applications

TSMC continuously improves its Chip-on-Wafer-on-Substrate (CoWoS) technology. Today, the company is announcing that, through a collaboration with Broadcom, it is introducing an enhanced CoWoS packaging technology supporting the full 2x reticle size interposers, the largest announced to date. As part of the collaboration, Broadcom defined the top-die, interposer, and HBM configuration while TSMC developed the packaging manufacturing process. With the current i193 and EUV lithography steppers, you are looking at a maximum reticle field size of 26 mm by 33 mm or 858 mm². The new CoWoS enhancement enables chips 1716 mm² in order to enable the larger HPC applications such as HBM-based CPUs and GPUs. TSMC says that the new CoWoS packaging technology is being ready to support TSMC’s upcoming 5-nanometer node.

TSMC says the new CoWoS packaging technology can accommodate multiple logic dies as well as up to six high-bandwidth memory stacks. As far as memory goes, up to 96 GiB of HBM memory or 16 GiB a stack is supported with bandwidths of up to 2.7 TB/s which is roughly 2.2x the currently highest memory bandwidth. For example, Intel’s recently axed Spring Crest has a memory bandwidth of 1.23 TB/s while NEC’s SX-Aurora tops out at 1.22 TB/s. Support for larger memory comes from Samsung’s new HBM2E dies which goes under the Flashbolt brand. These dies double the density to 16 gigabits per die and with each supporting up to 3.2 GT/s, this translates to 2.46 TB/s for six stacks.

The extension to full 2x reticle is largely a very evolutional announcement. TSMC has been increasing the capabilities of its CoWoS technology for the past half-decade. By 2016 TSMC extended the size of largest CoWoS products to 1.5x. This has enables products such as the Nvidia Pascal P100 to extend to 4 HBM stacks with a 1200 mm² interposer. By 2017 TSMC increased that to 1.75x with products such as NEC SX-Aurora and the V100. Finally with today’s announcement, TSMC is reaching the 2x reticle size.

Looking a little further, TSMC has plans for even larger interposers with up to 3x the reticle size or even larger. At three times the reticle, this means interposers of up to 2574 mm². Last year the company showed off a massive 7.5 x 7.5 cm² package with two large 600 mm² dies along with eight stacks of HBM memory. No word on when we can expect the technology to make it to market.

https://fuse.wikichip.org/news/3377...icle-cowos-for-next-gen-5nm-hpc-applications/

https://www.techpowerup.com/264433/...-with-worlds-first-2x-reticle-size-interposer

O chip parece ser da Broadcom.

 

[Dark Kaeser]

Mas a imagem colocada pode induzir em erro, o do anúncio é de um interposer ~1700mm² (1716 mm² segundo o que está no artigo).

 

[Nemesis11]

Um pequeno artigo sobre o 5 nm da TSMC.

TSMC execution has been remarkable the last couple of nodes. Since their 16 nm node, each process node has been ramping quicker than its predecessor. N7 was the company’s quickest-ramping node with fastest defect density reduction ever. TSMC says it expects its N5 node to ramp even quicker. 5-nanometer entered risk production in March 2019. The process is expected to ramp in Q2 this year – likely in April or May. When ramped, this will be the densest process in terms of both transistor density and SRAM density – leapfrogging both Samsung and Intel. Samsung 5-nanometer is only slightly denser than their 7-nanometer and is not competitive with TSMC 5 nm. Samsung’s next big jump is their 3-nanometer node. Intel will likely capture the density lead with their 7-nanometer node, however, that node isn’t coming until late next year – a solid 1.5 years behind.

TSMC 5-nanometer node will be ramping at Fab 18, a new 12-inch EUV GigaFab being constructed in three phases. Phase one finished in early 2018 which is where 5-nanometer is ramping. Phase 2 started a little later and is expected to enter volume production in 2020 as well. The final phase, Phase 3, started in 2019 and is planned for volume production in 2021. Fab 18 will also be the future home of their 3-nanometer process which is planned for 2022.

https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/

 

[Dark Kaeser]

Edited Transcript of 2330.TW earnings conference call or presentation 16-Apr-20 6:00am GMT

Now let me talk about our N5 status. N5 is already in volume production with good yield. Our N5 technology is a full node stride from our N7, with 80% logic density gain and about 20% speed gain compared with N7. N5 will adopt EUV extensively. We expect a very fast and smooth ramp of N5 in the second half of this year driven by both mobile and HPC applications. We'll reiterate 5-nanometer will contribute about 10% of our wafer revenue in 2020. N5 is the foundry industry's most advanced solution with best PPA. We observed a higher number of tape-outs, as compared with N7 at the same period of time. We will offer continuous enhancements to further improve the performance, power and density of our 5-nanometer technology solution into the future as well. Thus, we are confident that 5-nanometer will be another large and long-lasting node for TSMC.

https://finance.yahoo.com/news/edited-transcript-2330-tw-earnings-161634209.html

 

[Dark Kaeser]

2020 Status
At the end of 2019, Samsung and TSMC both began risk production of 5nm processes and both processes are in production in 2020.

5nm is where TSMC really stakes out a density lead, TSMC’s 5nm process has a reported 1.84x density improvement versus 7nm whereas Samsung’s 5nm process is only a 1.33x density improvement. Figure 5 compares Intel’s 10nm process to Samsung and TSMC’s 5nm processes since 10nm is still Intel’s densest process in 2020.

https://semiwiki.com/semiconductor-...-tsmc-maintain-their-process-technology-lead/

 

[Dark Kaeser]

Sal para a mesa do canto... fazfabor

Tradução por um blogger de taiwan

https://twitter.com/chiakokhua/status/1259796708050911232

 

[Luka_]

Bem, a Intel a produzir na TSMC. Quem diria.

 

[V3ctor]

GPUs... Não me admira...

CPUs nas fábricas da Intel, GPUs fora... Não vejo nada de extraordinário.

 

[JPgod]

Intel a fazer outsourcing é mesmo interessante...

Resta saber se será apenas GPU discrette ou os IGPs tb serão 5nm e fazerem um MCM a lá zen2

 

[Nemesis11]

Bem, o slide não diz bem isso. Diz "Intel: Xe-architecture GPUs, or FPGA". Traduzindo, GPUs ou FPGAs.
A antiga Altera, que a Intel comprou, tinha a produção na TSMC. Acho que os mais recentes, já são produzidos nas fábricas da Intel.
Dito tudo isto, já tinham aparecido rumores que a Intel iria produzir, pelo menos alguns dos GPUs a 7nm, na TSMC.