2_kamikaze_2
Power Member
Dúvido que se acabe com o x86 pelo menos nos próximos anos longos anos, muito longos anos, mas basta perceber a evolução que tem existido do lado dos arm para perceber que é preciso fazer alguma coisa
IMO não faz sentido nenhum, mesmo que isso acontecesse ias ver que depois iam descobrir outras vulnerabilidades por outros métodos etc... O que fazia sentido era nunca terem feito backdoors agora que a porta foi aberta não tem fim, a solução é repensar a arquitectura futura, se calhar o x86 está demasiado velho para andar a ser remendado como se fosse a camara de um peneu...
Dúvido que se acabe com o x86 pelo menos nos próximos anos longos anos, muito longos anos, mas basta perceber a evolução que tem existido do lado dos arm para perceber que é preciso fazer alguma coisa
Summary
Intel recently announced that they have completed software validations and have started to release new microcode for current CPU platforms in reaction to the following threats:
This new release includes a microcode update from Intel for the following CPUs.
- Spectre Variant 3a (CVE-2018-3640: "Rogue System Register Read (RSRE)")
- Spectre Variant 4 (CVE-2018-3639: "Speculative Store Bypass (SSB)")
- L1TF (CVE-2018-3620, CVE-2018-3646: "L1 Terminal Fault")
Important Install this update for the listed processors only.
Um 9900k, por exemplo, que vulnerabilidades conhecidas (actualmente) apresenta?
https://hardenedbsd.org/article/op/2018-12-17/stable-release-hardenedbsd-stable-12-stable-v1200058
- Symmetric Multi-Threading (SMT) disabled by default (re-enable by setting machdep.hyperthreading_allowed to 1 in loader.conf(5)).
Um 9900k, por exemplo, que vulnerabilidades conhecidas (actualmente) apresenta?
É o segundo BSD a desabilitar SMP por default.
This security shortcoming can be potentially exploited by malicious JavaScript within a web browser tab, or malware running on a system, or rogue logged-in users, to extract passwords, keys, and other data from memory. An attacker therefore requires some kind of foothold in your machine in order to pull this off. The vulnerability, it appears, cannot be easily fixed or mitigated without significant redesign work at the silicon level.
The researchers – Saad Islam, Ahmad Moghimi, Ida Bruhns, Moritz Krebbel, Berk Gulmezoglu, Thomas Eisenbarth and Berk Sunar – have found that "a weakness in the address speculation of Intel’s proprietary implementation of the memory subsystem" reveals memory layout data, making other attacks like Rowhammer much easier to carry out.
The researchers also examined Arm and AMD processor cores, but found they did not exhibit similar behavior.
SPOILER describes a technique for discerning the relationship between virtual and physical memory by measuring the timing of speculative load and store operations, and looking for discrepancies that reveal memory layout.
"The root cause of the issue is that the memory operations execute speculatively and the processor resolves the dependency when the full physical address bits are available," said Moghimi. "Physical address bits are security sensitive information and if they are available to user space, it elevates the user to perform other micro architectural attacks."
They just don't do it all that well. "The root cause for SPOILER is a weakness in the address speculation of Intel’s proprietary implementation of the memory subsystem which directly leaks timing behavior due to physical address conflicts," the paper explains.
"Our algorithm, fills up the store buffer within the processors with addresses that have the same offset but they are in different virtual pages," said Moghimi. "Then, we issue a memory load that has the same offset similarly but from a different memory page and measure the time of the load. By iterating over a good number of virtual pages, the timing reveals information about the dependency resolution failures in multiple stages."
SPOILER, the researchers say, will make existing Rowhammer and cache attacks easier, and make JavaScript-enabled attacks more feasible – instead of taking weeks, Rowhammer could take just seconds. Moghimi said the paper describes a JavaScript-based cache prime+probe technique that can be triggered with a click to leak private data and cryptographic keys not protected from cache timing attacks.
Mitigations may prove hard to come by. "There is no software mitigation that can completely erase this problem," the researchers say. Chip architecture fixes may work, they add, but at the cost of performance.
Intel is said to have been informed of the findings on December 1, 2018. The chip maker did not immediately respond to a request for comment. The paper's release comes after the 90 day grace period that's common in the security community for responsible disclosure.
Moghimi doubts Intel has a viable response. "My personal opinion is that when it comes to the memory subsystem, it's very hard to make any changes and it's not something you can patch easily with a microcode without losing tremendous performance," he said.
"So I don't think we will see a patch for this type of attack in the next five years and that could be a reason why they haven't issued a CVE."