Ainda não é a apresentação oficial do sucessor do core "Bobcat", mas hoje durante a conferência Hot Chips, foram avançados alguns dados:
De relembrar qual o objectivo deste core "Jaguar", que serão usados na plataforma "Kabini" e "Temash"
http://semiaccurate.com/2012/08/28/amd-let-the-new-cat-out-of-the-bag-with-the-jaguar-core/Today AMD starts the long process of revealing this chips, but things like the speeds, die areas, and most of the uncore were not revealed. In fact, AMD didn’t even mention that it is a 28nm part.
So what did they talk about? Jaguar supports one to four cores, has up to 2MB of L2 cache, and supports most of the latest instruction sets. The x86 additions that Jaguar adds to the Bobcat baseline are SSE4.1, SSE4.2, AES, CLMUL, MOVBE, AVX, XSAVE, XSAVEOPT, FC16, and BMI1. It also now supports 40 bits of physical memory, that would be 1TB or so, but the chip only has a one memory channel.
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On the FP side, things are very different. Like Bobcat, the decoder can still issue two instructions per clock to two FP pipelines. Bobcat had 64-bit wide FP units, so 128-bit SSE instructions had to be processed with two passes though that pipe. This hurt performance but took less die area. With the shrink to 28nm, Jaguar’s cores have a lot more area to play with, so the FP pipes were widened to 128-bits for one pass SSE execution.
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More profound is the IPC differences while running the different code bases used to measure the power gating. AMD is claiming more than 10% frequency gains with Jaguar, and the IPC goes up more than 15%. In total, those gains are pretty significant, and if the net SoC power comes in lower too, that is a clear win.
http://www.eetimes.com/electronics-news/4394786/AMD-s-Jaguar-packs-four-cores-in-one-for-mobileAs for the Jaguar core, AMD predicts that based on simulations it will deliver more than ten percent higher frequencies and more than 15 percent more instructions per clock than Bobcat, its current low power x86 core. Jaguar will appear in 2013 in AMD’s Kabini SoC for low-power notebooks and in Temash, AMD’s first sub-5W SoC, aimed at tablets.
The chip sports a re-designed load/store unit and an expanded 128-bit floating point unit. It includes several new instructions to support AES encryption, accelerate media processing and switch big/little endian structures for embedded systems. But the most novel aspect of the new core is its use of four x86 cores in a single unit sharing one L2 cache.
“From a core perspective we will call this a four-core unit that forms the building block of an SoC design,” said Jeff Rupley, an AMD Fellow and chief architect of Jaguar. “It’s possible to fuse off some cores for lower end or lower power designs,” he said.
AMD found sharing one 1-2 Mbyte L2 cache among the cores saves silicon area over using four private caches. It also provides a performance boost when only one or two single-threaded cores are running and can then access a larger memory pool.
“Generally the larger cache outweighs the latency” of needing an L2 cache interface, Rupley said. “There could be an app where the latency increase defeats the capacity boost, but across a large swath of apps, there’s a pretty positive uplift,” he said.
De relembrar qual o objectivo deste core "Jaguar", que serão usados na plataforma "Kabini" e "Temash"