Memória DDR6, LPDDR6, GDDR7, HBM3

[Nemesis11]

Para quê andar a pensar se é melhor comprar DDR4 ou DDR5, quando vem aí DDR6?

Do Tech Day 2021 da Samsung.

DDR6:

With DDR6 the doubling continues and for DDR6 up to 12,800 MT / s are planned accordingly, with DDR6 + it should be 17,000 MT / s. Samsung is working together with other JEDEC members from circles of DRAM and SoC manufacturers on the completion of the DDR6 standard, which according to current planning is expected in 2024. One of the chief engineers at SK Hynix had indicated in advance that it could take a little longer with this generation . Samsung now admits that it is still in the " early phase of development " of DDR6.

The number of memory channels (channel) per module is to increase to four with DDR6 and thus double again compared to DDR5. The number of memory banks increases by a factor of two to 64, which in turn means four times as much as DDR4.

LPDDR6:

At the same time, work is continuing on the more economical variant Low Power DDR (LPDDR) for mobile devices such as smartphones. Here LPDDR5 (up to 6,400 MT / s) or LPDDR5X (up to 8,500 MT / s) is the current state of development. Samsung already presented its new LPDDR5X last week . At the beginning of 2022, Samsung plans to mass-produce the LPDDR5X using the 1a-nm process.

In addition to more performance, the focus here is primarily on energy efficiency, which is improved with every generation. LPDDR6 should achieve up to 17,000 MT / s, but work another 20 percent more efficiently.

GDDR7:

Samsung describes its GDDR6 , which is primarily intended for graphics applications, with 18,000 MT / s as " currently the fastest DRAM in the world ". Samsung plans to increase this to 24,000 MT / s in the 1z nm process this month and is calling this level GDDR6 +. The successor GDDR7 is still on the roadmap without a public appointment. With this, the throughput should increase by a third to 32,000 MT / s. Another innovation in GDDR7 is a " real-time error protection feature ", which Samsung has not yet explained in more detail.

HBM3:

Just last month, SK Hynix announced the completion of its first HBM3 with 819 GByte / s , which will be used in products next year. The third generation of high-bandwidth memory , a DRAM variant trimmed for the highest transfer rates with stacked dies and short cable paths, is also on the agenda at Samsung. The manufacturer speaks of 800 GB / s for HBM3 and 450 GB / s for the intermediate level HBM2E. Samsung plans to mass-produce HBM3 in the second quarter of 2022 and emphasizes its suitability for AI applications.

https://www-computerbase-de.transla...r_sl=de&_x_tr_tl=en&_x_tr_hl=bg&_x_tr_pto=nui

 

[ToTTenTranz]

Se virmos as primeiras DDR6 em 2024 então a DDR5 será o standard mais curto de sempre.

O que faz algum sentido, já que nos últimos anos vimos as LPDDRx a ultrapassar largamente as DDRx. o que sugere que as últimas estão a ficar demasiado para trás.

 

[Bodygard]

A DDR5 demorou tanto tempo a chegar que agora passam é já às seguintes...

 

[Dark Kaeser]

JEDEC Publishes GDDR7 Memory Spec: Next-Gen Graphics Memory Adds Faster PAM3 Signaling & On-Die ECC

“JESD239 GDDR7 marks a substantial advancement in high-speed memory design,” said Mian Quddus, JEDEC Board of Directors Chairman. “With the shift to PAM3 signaling, the memory industry has a new path to extend the performance of GDDR devices and drive the ongoing evolution of graphics and various high-performance applications.”

As previously revealed, the biggest technical change with GDDR7 comes with the switch from two-bit non-return-to-zero (NRZ) encoding on the memory bus to three-bit pulse amplitude modulating (PAM3) encoding. This change allows GDDR7 to transmit 3 bits over two cycles, 50% more data than GDDR6 operating at an identical clockspeed. As a result, GDDR7 can support higher overall data transfer rates, the critical component to making each generation of GDDR successively faster than its predecessor.

The first generation of GDDR7 is expected to run at data rates around 32 Gbps per pin, and memory manufacturers have previously talked about rates up to 36 Gbps/pin as being easily attainable. However the GDDR7 standard itself leaves room for even higher data rates – up to 48 Gbps/pin – with JEDEC going so far as touting GDDR7 memory chips "reaching up to 192 GB/s [32b @ 48Gbps] per device" in their press release. Notably, this is a significantly higher increase in bandwidth than what PAM3 signaling brings on its own, which means there are multiple levels of enhancements within GDDR7's design.

Digging deeper into the specification, JEDEC has also once again subdivided a single 32-bit GDDR memory chip into a larger number of channels. Whereas GDDR6 offered two 16-bit channels, GDDR7 expands this to four 8-bit channels. The distinction is somewhat arbitrary from an end-user's point of view – it's still a 32-bit chip operating at 32Gbps/pin regardless – but it has a great deal of impact on how the chip works internally. Especially as JEDEC has kept the 256-bit per channel prefetch of GDDR5 and GDDR6, making GDDR7 a 32n prefetch design.

The net impact of all of this is that, by halving the channel width but keeping the prefetch size the same, JEDEC has effectively doubled the amount of data that is prefetched per cycle of the DRAM cells. This is a pretty standard trick to extend the bandwidth of DRAM memory, and is essentially the same thing JEDEC did with GDDR6 in 2018. But it serves as a reminder that DRAM cells are still very slow (on the order of hundreds of MHz) and aren't getting any faster. So the only way to feed faster memory buses is by fetching ever-larger amounts of data in a single go.

The change in the number of channels per memory chip also has a minor impact on how multi-channel "clamshell" mode works for higher capacity memory configurations. Whereas GDDR6 accessed a single memory channel from each chip in a clamshell configuration, GDDR7 will access two channels – what JEDEC is calling two-channel mode. Specifically, this mode reads channels A and C from each chip. It is effectively identical to how clamshell mode behaved with GDDR6, and it means that while clamshell configurations remain supported in this latest generation of memory, there aren't any other tricks being employed to improve memory capacity beyond ever-increasing memory chip densities.

https://www.anandtech.com/show/21287/jedec-publishes-gddr7-specifications-pam3-ecc-higher-density