Processador Risc-V

[Dark Kaeser]

Invariavelmente isto vai acabar por aparecer, por isso, mais um tópico, para mais uma ISA para CPU.

Para quem se quiser inteirar

https://riscv.org/about/

 

[Dark Kaeser]

Entretanto a SiFIve lançou uma nova development board

https://www.sifive.com/blog/the-heart-of-risc-v-development-is-unmatched

Spoiler

James Prior a.k.a. CavemanJim antigo Product Manager da AMD, estes gajos andam por todo o lado

SiFive Is Launching The Most Compelling RISC-V Development Board Yet

https://www.phoronix.com/scan.php?page=article&item=sifive-riscv-unmatched&num=1

 

[Dark Kaeser]

XuanTie C906 based Allwinner RISC-V processor to power $12+ Linux SBC’s

As far as I understand companies are still under NDA with Allwinner, so they can divulge too much. But here’s what the $12.5 Sipeed Linux RISC-V board specifications should look like based on public information available at this stage:

• SoC – Unnamed Allwinner single-core XuanTie C906 64-bit RISC-V (RV64GCV) processor @ up to 1 GHz; 22nm manufacturing process
• GPU – 2D accelerator only (similar to what is found in Allwinner V3s)
• VPU – H.265/H.264
• System Memory – 64MB to 256MB DDR3 (PoP); external memory version may also be available
• Storage – MicroSD card socket
• Video Output / Display I/F – HDMI, RGB LCD
• Camera I/F – DVP and MIPI CSI
• Networking – GMAC (Gigabit Ethernet MAC), optional WiFi and Bluetooth module
• USB – USB host and OTG

https://www.cnx-software.com/2020/1...nner-risc-v-processor-to-power-12-linux-sbcs/
13$ mas Single Core e sem 3D

 

[Nemesis11]

2.4 Drystone MIPS/Mhz @ 1 Ghz = 2400 DMIPS.

Comparação com outras SBCs, incluindo os RPIs:

https://www.techrepublic.com/articl...review-this-board-really-can-replace-your-pc/

2400 DMIPS andaria ali pela performance do RPi 3, mas é preciso ter em conta que este benchmark é single thread e o RPi 3 tem 4 Cores, enquanto este processador RISC-V da Allwinner é Single Core.
Seja como for, é bastante interessante.

 

[Dark Kaeser]

O processador tecnicamente até é da *****, da sua divisão T-Head, o mesmo tinha sido apresentado na Hot Chips deste ano, embora a ***** tenha desenvolvido o chip "em clusters" com 1 a 4 cores por cluster, a versão apresentada tinha 16 cores - o Xuantie 910, mas ainda estará para entrar em produção na TSMC @12nm.

06:10PM EDT - Xuantie-902 (M0+ like) with hardware TEE up to Xuantie-910

06:10PM EDT - 903, 907,908 coming

https://www.anandtech.com/show/15991/hot-chips-2020-live-blog-*****-xuantie910-riscv-cpu-300pm-pt

Esta colaboração entre a ***** e Allwinner, deve ser provavelmente o 902, e num processo mais antigo a 22nm (assim de repente a úncia com processo a 22nm era a Intel e a IBM, a Globalfoundries é que tem um 22FDX - 22nm FDSOI).

A performance também foi falada

se bem que não entendi se os números apresentados se baseiam numa extrapolação da simulação do chip num FPGA, ou na versão do chip ainda a 28nm HPC+ da TSMC que eles aparentemente também têm de momento, dado que o chip a 12nm ainda não estaria em produção.

06:25PM EDT - Here's an AI workload on an FPGA simulation of X910

06:26PM EDT - FPGA X910 already deployed in ***** cloud

06:27PM EDT - FPGA runs at 200 MHz

***** On The Bleeding Edge Of RISC-V With XT910

https://3s81si1s5ygj3mzby34dq6qf-wp...content/uploads/2020/08/*****-superscaler.png
https://3s81si1s5ygj3mzby34dq6qf-wp...ontent/uploads/2020/08/*****-interconnect.png
https://3s81si1s5ygj3mzby34dq6qf-wpengine.netdna-ssl.com/wp-content/uploads/2020/08/*****-AI.png
https://www.nextplatform.com/2020/08/21/*****-on-the-bleeding-edge-of-risc-v-with-xt910/

EDIT: esqueci-me do Whitepaper @ 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)

Xuantie-910: A Commercial Multi-Core 12-StagePipeline Out-of-Order 64-bit High PerformanceRISC-V Processor with Vector Extension
https://conferences.computer.org/isca/pdfs/ISCA2020-4QlDegUf3fKiwUXfV0KdCm/466100a052/466100a052.pdf

 

[Nemesis11]

Essa versão de facto é melhor. Eles comparam sempre ao A73 da ARM, o que já é bastante bom.

 

[Dark Kaeser]

Ainda falta é saber o TDP/consumo, mas a ver vamos.

 

[Nemesis11]

Foi lançado o "BBC Doctor Who HiFive Inventor Coding Kit", com o processador SiFive RISC-V FE310-G003, numa colaboração entre a BBC, Tynker e SiFive, para o mercado educativo.

https://www.hifiveinventor.com/

 

[Dark Kaeser]

Et tu BBC

Está bem que ARM já não é inglesa, mas ainda assim são 75$.

 

[Dark Kaeser]

BeagleV - Beagle Board Risc-V

https://beagleboard.org/beaglev


$119+ BeagleV powerful, open-hardware RISC-V Linux SBC targets AI applications

BeagleBoard.org foundation, Seeed Studio, and Chinese fabless silicon vendor Starfive partnered to design and launch the BeagleV SBC (pronounced Beagle Five) powered by StarFive JH7100 dual-core SiFive U74 RISC-V processor with Vision DSP, NVDLA engine, and neural network engine for AI acceleration.

BeagleV specifications:

• SoC – StarFive JH7100 Vision SoC with:
  • RISC-V U74 dual-core with 2MB L2 cache @ 1.5 GHz
  • Vision DSP Tensilica-VP6 for computing vision
  • NVDLA Engine 1 core (configuration 2048 MACs @ 800MHz – 3.5 TOPS)
  • Neural Network Engine (1024MACs @ 500MHz – 1 TOPS)
  • VPU – H.264/H.265 decoder up to 4Kp60, dual-stream decoding up to 2Kp30
  • JPEG encoder/decoder
  • Audio Processing DSP and sub-system
• System Memory – 4GB or 8GB LPDDR4
• Storage – MicroSD card slot
• Video output
  • 1x HDMI port up to 1080p30
  • 1x MIPI DSI interface up to 4Kp30
  • MIPI-CSI TX for video output after ISP and AI processing
• Camera
  • Dual channels of ISP, each channel support up to 4K @ 30FPS
  • 2 x MIPI-CSI Rx
• Audio – 3.5mm audio jack
• Connectivity – 1x Gigabit Ethernet, 2.4 GHz 802.11b/g/n WiFi 4, and Bluetooth 4.2
• USB – 4x USB 3.0 Ports
• Expansion – 40-pin GPIO header with 28 x GPIO, I2C, I2S, SPI, UART
• Security – Support TRNG and OTP
• Misc – Reset and power buttons
• Power Supply – 5V/3A via USB Type-C port

One obvious item missing from the specifications is a GPU, and I was told while the first batch scheduled in March will be GPU less, but the next batch – slated to be manufactured in September – will come with an Imagination Technologies GPU.

https://www.cnx-software.com/2021/0...are-risc-v-linux-sbc-targets-ai-applications/

 

[Nemesis11]

Bastante interessante, mas GPUs da Imagination e Sistemas Operativos Open Source................Medo.
A GMA500 foi o pior GPU que tive a nível de suporte de drivers. Até em Windows era terrível. Em Linux? LOL.

 

[skandal]

Talvez mandem technical papers para a malta do Kernel para ver se alguém se digna a suportar?

 

[Dark Kaeser]

Já vai quase um ano, não faço ideia do progresso, mas

"We need you to join the Linux driver development team and put your software development skills to the test. You will focus on developing a new Linux open source graphics driver stack, including Mesa and kernel-mode drivers. You will be a member of a small team, working alongside other software teams implementing the existing driver stack for PowerVR graphics hardware."

https://www.phoronix.com/scan.php?page=news_item&px=Imagination-New-Open-Graphics

E ainda em Novembro

Imagination’s PowerVR GPU Driver (DDK v1.13 release onwards) supports RISC-V as a target application processor and will be easily integrated with the PicoRio single-board computer platform. Imagination is also creating a new open-source GPU driver to provide a complete, up-streamed open-source kernel and user-mode driver stack to support Vulkan® and OpenGL® ES within the Mesa framework.

https://riscv.org/blog/2020/11/picorio-the-raspberry-pi-like-small-board-computer-for-risc-v/

 

[Dark Kaeser]

Android 10 ported to RISC-V board powered by ***** T-Head XuanTie C910 Processor

The demo above runs on ICE EVB powered by a XuanTie C910 based high-performance SoC board developed by T-Head. Specifically, the ICE SoC integrates two XuanTie C910 cores (RV64) @ 1.2 GHz, one other XuanTie C910V core @ 1.2 GHz with vector extensions, a single-core 3D GPU core [Update: it’s a Vivante GC8000UL GPU], DDR4 memory support, a GMAC (Gigabit Ethernet) interface, as well as 4Kp60 HEVC/AVC/JPEG video decoding. The display resolution appears limited to 1920×1080 however.

https://www.cnx-software.com/2021/0...ard-powered-by-*****-t-head-xuantie-c910-soc/

 

[Dark Kaeser]

E agora um GPU, aparentemente mais um, a usar.... ISA Risc-V

A group of enthusiasts are proposing a new set of graphics instructions designed for 3D graphics and media processing. These new instructions are built on the RISC-V base vector instruction set. They will add support for new data types that are graphics specific as layered extensions in the spirit of the core RISC-V instruction set architecture (ISA). Vectors, transcendental math, pixel, and textures and Z/Frame buffer operations are supported. It can be a fused CPU-GPU ISA. The group is calling it the RV64X as instructions will be 64-bit long (32 bits will not be enough to support a robust ISA).

The team says their motivation and goals are driven by the desire to create a small, area-efficient design with custom programmability and extensibility. It should offer low-cost IP ownership and development, and not compete with commercial offerings. It can be implemented in FPGA and ASIC targets and will be free and open source. The initial design will be targeted to low-power microcontrollers. It will be Khronos Vulkan-compliant, and over time support other APIs (OpenGL, DirectX and others).

The final hardware will be a RISC-V core with a GPU functional unit. To the programmer it will look like a single piece of hardware with 64-bit long instructions coded as scalar instructions. The programming model is an apparent SIMD, that is, the compiler generates SIMD from prefixed scalar opcodes. It will include variable-issue, predicated SIMD backend, vector front-end, precise exceptions, branch shadowing and much more. There won’t be any need for RPC/IPC calling mechanism to send 3D API calls to/from unused CPU memory space to GPU memory space and vice-versa, says the team. And it will be available as 16-bit fixed point (ideal for FPGAs), as well as 32-bit floating point (ASICs or FPGAs).

The design will employ the Vblock format (from the Libre GPU effort):

• It is a bit-like VLIW (only not really)
• A block of instructions is pre-fixed with register tags which give extra context to scalar instructions within the block
• Sub-blocks include: vector length, swizzling, vector/width overrides and predication.
• All this is added to scalar opcodes
• There are no vector opcodes (and no need for any)
• In the vector context, it goes like this: if a register is used by a scalar opcode, and the register is listed in the vector context, vector mode is activated
• Activation results in a hardware-level for-loop issuing multiple contiguous scalar operations (instead of just one).
• Implementers are free to implement the loop in any fashion they desire: SIMD, multi-issue, single-execution.

RV64X block diagram

The RV64X reference implementation will include:

• Instruction/Data SRAM Cache (32KB)
• Microcode SRAM(8KB)
• Dual Function Instruction Decoder
  • Hardwired implementing RV32V and X
  • Micro-coded Instruction Decoder for custom ISA
• Quad Vector ALU (32 bits/ALU—fixed/float)
• 136-bit Register Files (1K elements)
• Special Function Unit
• Texture Unit
• Configurable local Frame Buffer

RV64X’s scalable design

https://www.eetimes.com/rv64x-a-free-open-source-gpu-for-risc-v/

 

[Nemesis11]

Acho que é a primeira SBC "barata" com Risc-V, à venda e disponível. RVBoards Nezha:

O Processador é o "Allwinner D1 XuanTie C906". Parece que é fabricado a 22 nm:

Specs:

• Allwinner D1 XuanTie C906 1 GHz single-core RISC-V 64-bit processor
• HiFi 4 DSP
• G2D 2D graphics accelerator
• 1GB DDR3 memory
• 256MB SPI NAND flash storage
• microSD card reader
• HDMI 1.4 (4K @ 30 Hz or 1080p @ 60 Hz)
• 3.5mm audio jackk
• Gigabit Ethernet
• WiFi 4
• Bluetooth 4.2
• 1 x USB 2.0 port
• 1 x USB Type-C OTG port
• 1 x USB Type-C 5V/2A power input
• 40-pin GPIO header
• MIPI DSI display & touch panel connector

https://www.cnx-software.com/2021/05/20/nezha-risc-v-linux-sbc/
https://liliputing.com/2021/05/nezha-is-a-99-single-board-pc-with-a-risc-v-processor.html

Parece que corre (pelo menos) Debian Sid e um fork de OpenWRT.
Comparado com um RPi4, está longe de ter um preço/performance competitvo, mas é um inicio.

 

[Dark Kaeser]

É possível, havia várias boards anunciadas com esse tal processador em processo mais antigo produzidas pela Allwiner, mas o SoC em si é desenvolvido e licenciado por um grupo Chinês, como disse algures em cima.

De resto irão começar a aparecer projectos para outras áreas, este de um empresa do UK para o mercado Open RAN (infraestrutura de redes móveis)

PicoCom tapes out multicore RISC-V OpenRAN chip for ORANIC board​

The PC802 chip combines 32 RISC-V cores and 3 CEVA vector processor cores with 25Mbits of SRAM. One chip can be used as the controller for 4G or 5G small cell, but four can also be used on a card to manage 16 remote radios from different suppliers. Two cards can handle 32 radio heads.

“The chip itself is on the point of tapeout for engineering lots on TSMC 12nm,” said Peter Claydon, president of PicoCom in Bristol.

https://www.eenewseurope.com/news/picocom-tapes-out-multicore-risc-v-openran-chip-oranic-board

 

[Dark Kaeser]

European Processor Initiative Announces EPAC1.0 RISC-V Test Chip Taped-out​

The test chip, shown in figure 1 below, contains four vector processing micro-tiles (VPU) composed of an Avispado RISC-V core designed by SemiDynamics and a vector processing unit designed by Barcelona Supercomputing Center and the University of Zagreb. Each tile also contains a Home Node and L2 cache, designed respectively by Chalmers and FORTH, that provide a coherent view of the memory subsystem. The Stencil and Tensor accelerator (STX) was designed by Fraunhofer IIS, ITWM and ETH Zürich, and the variable precision processor (VRP) by CEA LIST. These specialized accelerators are connected with very high-speed network on chip and SERDES technology from EXTOLL.

EPAC layout with VPU, STX and VRP accelerators with 25 mm2 in GF 22FDX technology

The EPAC design was finalized by Fraunhofer IIS for chip integration in GLOBALFOUNDRIES 22FDX low-power technology and will be integrated and evaluated in the FPGA-based board designed by FORTH, E4 and the University of Zagreb. The successful fabrication of EPAC will showcase the next step in accelerator-based green HPC computing.

https://www.hpcwire.com/off-the-wir...announces-epac1-0-risc-v-test-chip-taped-out/

 

[Nemesis11]

Chipmaker SiFive Is Said to Draw Intel Takeover Interest​

• Intel offered to acquire SiFive for more than $2 billion
• Talks are early and SiFive could chose to remain independent

SiFive Inc., a startup that designs semiconductors, has received takeover interest from investor Intel Corp., according to people familiar with the matter.

Intel offered to acquire SiFive for more than $2 billion, one of the people said, asking not to be identified because the matter is private.

The San Mateo, California-based company has been in talks with potential advisers on how to handle the takeover interest, the people added.

The company has received takeover offers from multiple parties other than Intel, one of the people said. It has also fielded offers for an investment, which could be a preferable route, the person added.

Discussions are early, there’s no guarantee any deal will be reached, and SiFive may choose to remain independent.

SiFive was last valued at around $500 million when it raised funds in 2020, according to data provider PitchBook.

A representative for Intel declined to comment. A representative for SiFive didn’t respond to requests for comment.

ARM Rival​

SiFive is a designer of chips that are based on the RISC-V architecture, an attempt to bring open-source standards to semiconductor design making it cheaper and accessible to customers.

Interest in SiFive has increased since Nvidia Corp. agreed in September to pay $40 billion for SoftBank Group Corp.’s Arm Ltd., which like SiFive, licenses chip and process designs.

SiFive Chief Executive Officer Patrick Little is a chip industry veteran. He joined SiFive last year from Qualcomm Inc. where he was a senior vice president in charge of their automotive business.

Read More: Silicon Valley’s Next Revolution Is Open Source Semiconductors

SiFive is seen as a potential beneficiary if Nvidia’s deal goes through because Arm’s customers are concerned the company might work less collaboratively with them, the people said.

The company’s investors include SK Hynix Inc., Spark Capital and Prosperity7 Ventures, the venture arm of Saudi Arabia’s state-owned energy producer Aramco. It also is backed by the venture arms of chipmaker Qualcomm and of hardware maker Western Digital Corp. It last raised $61 million in a funding round in 2020.

https://www.bloomberg.com/news/arti...ifive-is-said-to-draw-intel-takeover-interest

Bastante curioso.
A questão que se levanta é se isto é algo que vem de uma "Nova Intel", para atacar pelo flanco a ARM, nVidia e não só ou se é algo que vem de uma "Velha Intel" e serve para abafar potenciais futuros competidores.
De notar, que mesmo que falhe esta compra, nada impede a Intel de adoptar Risc-V. Nem a SiFive tem qualquer exclusivo a nível de Risc-V. Será sempre um negócio, se for para a frente, muito diferente da tentativa de compra da ARM por parte da nVidia.
Também de notar que pela notícia, a proposta da Intel não é a primeira e outras ofertas de compra e investimento já foram feitas.

 

[Dark Kaeser]

Tirando os chineses a SiFive é de facto "A" RISC-V.

Diria que tudo depende do interesse de quem gere os destinos da mesma, Cash In ou Cash Out, ambas referidas no artigo.

Aparentemente a empresa consegue atrair mais investimento se for essa a opção (Cash In), agora depende se os fundadores pretendem recuperar o investimento (Cash Out).

Honestamente só estou a ver a Intel a tratar isto como um "investimento", abafando um potencial competidor o mais cedo possível, ISA é o que não falta à Intel, tirando o x86, ARM, MIPS...