Processador Centaur x86 CPU com coprocessador AI

[Nemesis11]

Uma noticia surpresa. A Centaur, divisão de processadores da VIA, anunciou um novo processador x86 com um coprocessador para AI integrado.

Pontos a sublinhar:

• 8 cores @ 2.5 Ghz
• 16 MB cache
• Ring Bus
• 44 Lanes Pci-Ex
• 4 canais de memória DDR4 3200
• Suporte AVX-512
• TSMC 16 nm
• 195mm^2 (Coprocessador AI representa 34,4mm^2)
  
• Acelerador 4096-byte wide

Benchmark coprocessador no MLPerf:

https://centtech.com/ai-technology/
https://centtech.com/wp-content/uploads/PRSlides_1118_Release.pdf
https://semiaccurate.com/2019/11/18/centaurs-new-cpu-is-the-first-x86-with-an-ai-co-processor/

 

[Dark Kaeser]

esses gajos da VIA é como os zombies cada vez que parecem estar mortos não estão


Pela imagem parecem ter adoptado um desenho semelhante ao ring bus da Intel para ligar tudo, ao contrário da abordagem da AMD com os IF.
Os promenores são escassos, a ver os próximos desenvolvimentos.

 

[Dark Kaeser]

Centaur Unveils Its New Server-Class x86 Core: CNS; Adds AVX-512

Putting It All Together
Centaur is back, and it is back with a fairly powerful core. Since this is a technology reveal and a not a product announcement, Centaur is still withholding performance numbers, power ranges, and frequencies. Those will come next year as the company gets closer to productization. At a high level, the core exceeds the capabilities of Haswell but doesn’t quite get to Skylake. In many ways, it’s very comparable to AMD original Zen core but one-ups it in a number of areas. Centaur isn’t stopping here, the company has a focused roadmap to improve this core further.

https://fuse.wikichip.org/news/3099...new-server-class-x86-core-cns-adds-avx-512/2/

foxtrot... até a VIA conseguiu apanhar o Haswell.

 

[2_kamikaze_2]

pudera, o haswell saiu em 2013 e o skylake em 2015 nem um nem outro são leading edge de maneira alguma são designs muito antigos, mesmo o proprio sunny cove já esta pronto desde 2018 :S

 

[Nemesis11]

Interessante artigo. No papel parece ser ok.
160 mm^2 a 16 nm parece-me muito pequeno para um octa-core (sem o co-processador) com aquelas especificações. O chiplet de 8 cores do Zen 2 tem 74 mm^2 a 7nm, mas sem a parte de IO.
Estou curioso para ver performance e TDP.

 

[Dark Kaeser]

2ª Parte do artigo anterior por parte da wikichip

Centaur New x86 Server Processor Packs an AI Punch

Centaur already has silicon back and has made a number of public demonstrations. Current silicon demos operate at 2.5 GHz. It’s worth highlighting that on CHA, everything operates at that frequency – the ring, the x86 cores, and the NCORE. This makes Centaur’s NCORE, as far as we are aware, the highest clocked NPU on the market and by a sizable margin. A lot of effort has gone into ensuring everything meets that sustainable frequency, including AVX-512 workloads.

The NCORE itself has a very interesting design. It’s a whopping 32,768-bits wide SIMD VLIW machine. It’s a fully clean-sheet in-house design with a lot of specific enhancements for AI applictions. Centaur designed a whole software stack around this processor that uses the standard frameworks most people are already familiar with such as TensorFlow and in the future Pytorch. Centaur’s software will compile the model into two instruction streams – x86 code and the AI coprocessor code.

https://fuse.wikichip.org/news/3256/centaur-new-x86-server-processor-packs-an-ai-punch/

 

[Nemesis11]

Apenas umas fotos deste CPU

https://semiaccurate.com/2020/02/17/centaur-cha-x86-ai-cpu-pictured/

Por fora parece um Xeon E5, mas o core por dentro é bastante pequeno (195 mm2).

Se fiz bem as contas, acho que deve ter por volta de 2250 pinos.

 

[Dark Kaeser]

Mas afinal não era suposto ser BGA? Pela imagem fica a dúvida.

 

[eblain]

AMA: x86 CPU Design House Centaur Technology

Hi from Austin TX!

Come ask us about how we design x86 CPU's and our new AI co-processor. Our engineers will be answering the questions.

Learn more about the industry's first high-performance x86 SOC with server-class CPUs and integrated AI coprocessor technology.

Technical details disclosed in Linley Group's Microprocessor Report

We even have a documentary: Rise of the Centaur

We're starting.

Here's a CPU-Z screenshot and Windows 10 screenshot

 

[Nemesis11]

Mas afinal não era suposto ser BGA? Pela imagem fica a dúvida.

É BGA. Fiz as contas por alto pelos contactos.

 

[Dark Kaeser]

Fiquei na dúvida não só pela imagem, mas também se estava a confundir com o Zhaoxin.

 

[Nemesis11]

Um artigo mais a fundo, de um site japonês, sobre este Centaur CHA.

The motivation for developing CHA + Ncore is as shown in the image below. The original CHA seems to have been an SoC that aims to replace the one provided by Zhaoxin as the KX-6000 series , and its target is the server market.

The base CHA has the structure shown in the image below. This time, the explanation about the x86 core is almost finished with this slide, but it has an IPC equivalent to Haswell, 2.5 GHz drive 8 core + 16 MB L2 connected just like Intel's Core with Dual Ring Bus Is.

Vector operation is equivalent to AVX32768 (64 times that of Intel). I think it is a reasonable method to minimize the latency during computation by mixing RAM and Logic together

Benchmarks:

https://translate.google.com/transl...&u=https://ascii.jp/elem/000/004/010/4010926/

 

[Dark Kaeser]

VIA To Offload Parts of x86 Subsidiary Centaur to Intel For $125 Million​

As part of their third quarter earnings release, VIA Technologies has announced this morning that the company is entering into an unusual agreement with Intel to offload parts of VIA’s x86 R&D subsidiary, Centaur Technology. Under the terms of the murky deal, Intel will be paying Centaur $125 million to pick up part of the engineering staff – or, as the announcement from VIA more peculiarly puts it “recruit some of Centaur's employees to join Intel,” Despite the hefty 9-digit price tag, the deal makes no mention of Centaur’s business, designs, or patents, nor has an expected closing date been announced.

In the meantime, local media reports are equally as puzzling, as language barriers aside, apparently even the local press isn’t being given much in the way of concrete details. None the less, local media such as United Daily News is reporting that the Intel deal is indeed not a wholesale sale of Centaur’s team, and that VIA is retaining the Centaur business. So what Intel is getting out of this that’s worth $125 million is, for the moment, a mystery.

Meanwhile, given the overall lack of details, news of the acquisition raises a number of questions about the future of VIA’s x86 efforts, as well as just what Intel is getting out of this. If VIA isn’t selling the Centaur business, then does that mean they’re retaining their x86 license? And if Intel isn’t getting any IP, then what do they need with Centaur’s engineering staff? Does Intel want to make their own take on the CNS x86 core?

https://www.anandtech.com/show/1704...6-subsidiary-centaur-to-intel-for-125-million

 

[Nemesis11]

Under the terms of the murky deal, Intel will be paying Centaur $125 million to pick up part of the engineering staff – or, as the announcement from VIA more peculiarly puts it “recruit some of Centaur's employees to join Intel,” Despite the hefty 9-digit price tag, the deal makes no mention of Centaur’s business, designs, or patents, nor has an expected closing date been announced.

Que negócio mais mal explicado. Pagar 125 milhões de $ para poder contratar alguns dos empregados da Centaur, não faz qualquer sentido. A Intel poderia contratar essas pessoas sem passar pela Via ou se quisesse passar pela Via, nunca seria um valor desta dimensão.
Fico com a ideia que a forma como está escrito é por alguma razão de negócio ou legal. Talvez a Intel compra a Centaur (Pessoas, instalações, equipamento, etc), mas a Via fique com o IP e licença x86, ou só a licença x86 ou algo assim, por causa da Zhaoxin. Mas mesmo que seja isso, será que a Intel vê 125 milhões de $ em valor na Centaur, mesmo contando com o IP? Será que o negócio inclui a licença x86? Se sim, como fica a Zhaoxin?

Espero que alguém explique melhor este negócio. Dá forma como está escrito agora, não faz sentido.

O Ian tem um vídeo sobre este negócio, ainda com poucas certezas.

 

[MinisterOfSound]

Boas,

Cheira mal, mas não terá sido antes uma maneira de atrasar o desenvolvimento e assim andar mais uns anos a vender Intel na China?

Cumps

 

[Dark Kaeser]

The Last x86 Via Chip: Unreleased Next-Gen Centaur CNS Saved From Trash Bin, Tested​

Brutus' Centaur chip, which carries the CentaurHauls codename, has eight CNS cores at 2.2 GHz and 16MB of L3 cache. The frequency is static. The Geekbench 5 submission revealed that the processor seemingly resides in a socket similar to Intel's LGA2011 socket. It explains why the CHA looks shockingly identical to Intel's Core X-Series HEDT chips and even has four DDR4 memory channels at its disposal.

https://www.tomshardware.com/news/l...com&utm_campaign=socialflow&utm_medium=social

O artigo é baseado na info desta conta do tweeter, tem lá mais coisas engraçadas

https://twitter.com/i/web/status/1494420492312326152

 

[Dark Kaeser]

Centaur CHA’s Probably Unfinished Dual Socket Implementation​

If CPU cores on one socket want to access memory connected to another socket, they’ll have to go through a cross-socket link. That creates a setup with non-uniform memory access (NUMA). Crossing sockets will always increase latency and reduce bandwidth, but a good NUMA implementation will minimize those penalties.

Cross-Socket Latency​

Cross-Socket Bandwidth​

Final Words​

Servers require high core counts, lots of IO, and lots of memory bandwidth. They also need to support high memory capacity. CHA delivers on some of those fronts. It can support hundreds of gigabytes of memory per socket. Its quad channel DDR4 memory controller and 44 PCIe lanes give adequate but not outstanding off-chip bandwidth. CHA is also the highest core count chip created by Centaur. But eight cores is a bit low for the server market today. Dual socket support could partially mitigate that.

Unfortunately, the dual socket work appears to be unfinished. CHA’s low cross socket bandwidth will cause serious problems, especially for NUMA-unaware workloads. It also sinks any possibility of using the system in interleaved mode, where accesses are striped across sockets to provide more bandwidth to NUMA-unuaware applications at the expense of higher latency.

So what went wrong? Well, remember that cross socket accesses suffer extra latency. That’s common to all platforms. But achieving high bandwidth over a long latency connection requires being able to queue up a lot of outstanding requests. My guess is that Centaur implemented a queue in front of their cross socket link, but never got around to validating it. Centaur’s small staff and limited resources were probably busy covering all the new server-related technologies. What we’re seeing is probably a work in progress.

Centaur has implemented the protocols and coherence directories necessary to make multiple sockets work. And they work with reasonably good latency. Unfortunately, the cross-socket work can’t be finished because Centaur doesn’t exist anymore, so we’ll never see CHA’s full potential in a dual socket setup.

https://chipsandcheese.com/2022/04/23/centaur-chas-probably-unfinished-dual-socket-implementation/

Os testes foram feitos na board acima do Brutus.

 

[Dark Kaeser]

https://twitter.com/i/web/status/1533164810765881344

Playing Cyberpunk 2077 on Centaur's unreleased CNS 8-core x86 Server CPU running at 2.5ghz​

 

[Dark Kaeser]

https://twitter.com/i/web/status/1534363669672259584

 

[Dark Kaeser]

https://twitter.com/i/web/status/1546808188946841600