Zealot
I quit My Job for Folding
There are at least 1.5 quarters left before AMD launches its 8th generation processors aka Hammer, and at the Platform Conference, which is now in progress, more and more details about the upcoming x86-64 CPUs keep cropping up.
As we already know, the first Athlon-64 (ClawHammer) and Opteron (SledgeHammer) CPUs will have 256KB and 1024KB L2 cache respectively. According to PCWatch, the future versions of these CPUs can easily get 512KB and 2MB L2 cache correspondingly. See these slides:
However, we have to point out that enhanced Hammer processors are very unlikely to appear in 2003, as they should be fast enough to compete successfully with the desktop Pentium 4 Northwood/Prescott and server Pentium 4 Nocona (667MHz system bus, 1MB L2 cache, HyperThreading, etc.). Besides, the core redesign will require pretty big financial investments not only from the development point of view but also from the production costs point of view.
It is very likely that the increase in the L2 cache size will happen as soon as they shift to finer manufacturing technology, which is expected some time in the end of 2003-beginning 2004. Some time ago we made a supposition that Hammer processors will move to finer manufacturing technology and at the same time acquire DDR-II SDRAM controller. If both speculations appear true, then we will be able to get a pretty significant performance improvement one day.
We should also mention that AMD guys claim they are working on a successor to AMD-8000. In particular, in the second half of 2004, we expect to see AMD-8111, an I/O controller supporting new functions and developed for HyperTransport 2.0 bus, and a bit later in 2004 – AMD-8131 also developed for HyperTransport 2.0 and supporting PCI-X 2.0.
Continuing the logical chain and keeping in mind the promising PCI-SIG plan, we can recall that Intel is going to introduce a new AGP version some time in 2005, which will work with 3GIO/PCI-Express protocols. As a result, AMD or its partners (if the company leaves the development of user PC chipsets for VIA and SiS by then) will have to work out a new graphics bus controller.
As we see, in 2004 AMD will be promoting HyperTransport 2.0 in the PC market. That is why bearing in mind the FSB frequency the upcoming Hammer CPUs will support, it seems quite logical to suppose that some time then these CPUs are also about to get the support of new data transfer protocols.
Since the introduction of the new system bus together with the changes in the memory controller will need some changes to be made to the platforms, it could be logical if AMD made all changes at once, so that not to follow in the footsteps of their major competitor who is constantly changing the processor socket pinout and introducing incompatible platform bases. However, it doesn’t make sense to argue here, as we have no evidence proving the compatibility of HyperTransport 1.0 and 2.0 yet.
All in all, we saw once again that x86-64 processors arrived to stay long. Within the next 2-3 years we shall expect some evolutionary changes, such as the implementation of finer manufacturing technology, increase in the L2 cache size, adoption of new faster memory types, and a shift to new data transfer bus. How will all these changes go, we have no idea yeat, unfortunately. So, let’s wait and see.
Fonte: http://www.xbitlabs.com/news/story.html?id=1027496035
As we already know, the first Athlon-64 (ClawHammer) and Opteron (SledgeHammer) CPUs will have 256KB and 1024KB L2 cache respectively. According to PCWatch, the future versions of these CPUs can easily get 512KB and 2MB L2 cache correspondingly. See these slides:
However, we have to point out that enhanced Hammer processors are very unlikely to appear in 2003, as they should be fast enough to compete successfully with the desktop Pentium 4 Northwood/Prescott and server Pentium 4 Nocona (667MHz system bus, 1MB L2 cache, HyperThreading, etc.). Besides, the core redesign will require pretty big financial investments not only from the development point of view but also from the production costs point of view.
It is very likely that the increase in the L2 cache size will happen as soon as they shift to finer manufacturing technology, which is expected some time in the end of 2003-beginning 2004. Some time ago we made a supposition that Hammer processors will move to finer manufacturing technology and at the same time acquire DDR-II SDRAM controller. If both speculations appear true, then we will be able to get a pretty significant performance improvement one day.
We should also mention that AMD guys claim they are working on a successor to AMD-8000. In particular, in the second half of 2004, we expect to see AMD-8111, an I/O controller supporting new functions and developed for HyperTransport 2.0 bus, and a bit later in 2004 – AMD-8131 also developed for HyperTransport 2.0 and supporting PCI-X 2.0.
Continuing the logical chain and keeping in mind the promising PCI-SIG plan, we can recall that Intel is going to introduce a new AGP version some time in 2005, which will work with 3GIO/PCI-Express protocols. As a result, AMD or its partners (if the company leaves the development of user PC chipsets for VIA and SiS by then) will have to work out a new graphics bus controller.
As we see, in 2004 AMD will be promoting HyperTransport 2.0 in the PC market. That is why bearing in mind the FSB frequency the upcoming Hammer CPUs will support, it seems quite logical to suppose that some time then these CPUs are also about to get the support of new data transfer protocols.
Since the introduction of the new system bus together with the changes in the memory controller will need some changes to be made to the platforms, it could be logical if AMD made all changes at once, so that not to follow in the footsteps of their major competitor who is constantly changing the processor socket pinout and introducing incompatible platform bases. However, it doesn’t make sense to argue here, as we have no evidence proving the compatibility of HyperTransport 1.0 and 2.0 yet.
All in all, we saw once again that x86-64 processors arrived to stay long. Within the next 2-3 years we shall expect some evolutionary changes, such as the implementation of finer manufacturing technology, increase in the L2 cache size, adoption of new faster memory types, and a shift to new data transfer bus. How will all these changes go, we have no idea yeat, unfortunately. So, let’s wait and see.
Fonte: http://www.xbitlabs.com/news/story.html?id=1027496035
