DURING YESTERDAY’S BRIEFING about technical and strategical decisions with Barcelona processors, the conversation turned into discussion about future features, the most notable mention being the future Fusion series.
When talking about future products, AMD execs told us that the company opened up the architecture in more ways than one. A senior AMD exec was talking about how company is planning to expand its partnering strategy, with
Torrenza coming first, and Fusion following later. Selected partnering companies are now developing products that will come to market during the 2008 and 2009 timeframe, most notably through the HTX expansion slot or simply Opteron processor Socket - but this is not the only way situation will evolve.
DAAMIT sees the future silicon as "lego bricks", putting different cores into different processors. AMD did not detail the brand names of these Lego CPUs, but the APU (Accelerated-Processing Unit) concept is rather interesting.
Fusion is not just CPU+GPU. There are different accelerators coming into frame for notebook, desktop and especially server parts
Graphics are not the only thing that could be integrated into Fusion processors either. While notebooks and desktops are poised to get graphics, the situation is rather different in the enterprise segment.
The integration of several specialised units was discussed, and if customers start demanding non-x86 units like java application accelerators or similar network processors, AMD might plan to deliver many more features in CPU silicon than originally expected.
Fusion between CPU and GPU is not just a fusion between two parts, internal architectures will be touched on both sides for discrete parts as well...
For AMD,
accelerators like XML, Java, Floating-Point are all very interesting targets indeed, but their implementation depends on customer interest (read: achievable sales volume), and company reps like Alberto Sacci and Giuseppe Amato confirmed to us that
future for AMD is combination between MCM and silicon integration, so it is possible that future products might be a combination between quad-core die (or even tri-core) with a massive number of specialized FP units -
we figure AMD is either going to assemble silicon with FP units from future ATI graphics chips for instance, or multiply the FP block inside the Bulldozer die. Read, double precision FP64 units adhering to IEEE specs and so on.
When it comes to the competition, we figure that Polaris demonstration of dumb FP units is going to be upgraded to x86 cores one way or another (sooner or later), and with Nehalem and Gesher sporting interesting integrated products (GbE NICs, graphics etc.), it seems that 2009 will be the beginning of yet another specialised war.
War of APUs, that is. µ