Processador Intel CPU 2018-2021 Roadmap Leaks Out

[Luka_]

Eles fizeram tanto dinheiro durante décadas que vão acabar fabless como a AMD e a nVidia.

 

[Nemesis11]

A compra da Tower Semiconductors está atrasada por causa do regulador Chinês. Por questões politicas, é capaz de não ser a melhor altura de fazer spinoff das Fabs, mesmo que isso faça sentido a nível de negócio para a Intel. Nesta altura, as fabs são o mais importante que a Intel tem e é praticamente um seguro de vida.

Entretanto, mais umas imagens e vídeo do Socket LGA7529.

Big boy.

 

[Dark Kaeser]

Sim as Fab é um dos activos que podem rentabilizar, se bem que já tinham feito uma tentativa que não correu muito bem.
A Tower sendo uma empresa "mais orientada para o cliente" fabless já tem uma série de contactos e know how, que a Intel levaria/levará algum tempo a construir.

Em relação ao dinheiro que a Intel durante anos recebeu também deu azo às várias desventuras, como os chips para os tablets, que sobreviveram enquanto a Intel esteve disposta a "pagar cerca de 3.5M$/ano", sendo que as outras incluíram a compra de empresas na tentativa de diversificar o negócio e que após uns anos "desapareciam".

 

[Dark Kaeser]

https://twitter.com/i/web/status/1641100579995893760

- Esmerald Rapids Q4 2023
- Granite Rapids (P-core Xeon) 1H 2024 @Intel3
- Sierra Forrest (E-core Xeon) 1H 2024

 

[Dark Kaeser]

https://twitter.com/i/web/status/1641117965113253888

 

[Nemesis11]

Não estou bem a ver como é que o Sierra Forest vai ser competitivo contra os 128 Cores Zen4c do Bergamo. É verdade que não se sabe ao certo o que vale o Zen4c, mas com SMT, não estou a ver como terá melhor performance. Talvez seja melhor a nível de Performance/Watt.

Wafer com dies do Sierra Forest (76 Cores por die, com 4 desabilitados? Parecem 19 conjuntos de 4(?) cores):

MCR DIMMs:

Along with upgrades to its CPU architecture, Intel is also disclosing for the first time that Granite Rapids will also come with a notable new memory feature: MCR DIMM support. First revealed by SK hynix late last year, Multiplexer Combined Ranks (MCR) DIMMs essentially gang up two sets/ranks of memory chips in order to double the effective bandwidth to and from the DIMM. With MCR, Intel and SK hynix are aiming to get data rates equivalent to DDR5-8800 (or higher) speeds, which would be a significant boon to memory bandwidth and throughput, as that's often in short supply with today's many-core chips.

As part of today’s presentation, Intel is showing off an early Granite Rapids system using MCR DIMMs to achieve 1.5TB/second of memory bandwidth on a dual socket system. Based on Intel’s presentation, we believe this to be an 12 channel memory configuration with each MCR DIMM running at the equivalent of DDR5-8800 speeds.

750 GB/s por Socket. Bem interessante.
Coincidencia ou não, não houve qualquer referencia a produtos com HBM, pelo menos nos Processadores.

 

[Dark Kaeser]

NOTA: antes que perguntem, o que a Intel vai vender é a divisão que vende servidores directamente a clientes, não sei qual o peso destas vendas dentro da divisão de servidores/datacenter.

BREAKING Intel Exiting the Server Business Selling to MiTAC​

In line with Intel’s continued efforts to prioritize investments in its IDM 2.0 strategy, we have made the difficult decision to exit our Data Center Solutions Group (DSG). As part of this plan, MiTAC, an edge-to-cloud IT solutions provider and longstanding ODM partner of DSG, will have the right to manufacture and sell products based on our designs. We are focused on ensuring the DSG team and its stakeholders are supported during this transition. (Source: Intel Spokesperson to STH)

This is not a rumor, it is happening.

For those who are unaware, Intel makes servers and fairly decent servers at that.

Intel made the servers usually with chassis sourced from Chenbro.

Intel sells its server systems outside of the US. Years ago (mid-2010’s) when I asked about this Intel told me they were popular in places like South America, but not necessarily a large competitor in the US market. These Intel PCSD systems also underpin server families like Intel’s Data Center Blocks and Data Center Systems (e.g. those certified for VMware, Microsoft Azure Stack, and Nutanix.) At one point, Intel was driving the DCB and DCS message hard, but that messaging has fallen off in the past several quarters.

https://www.servethehome.com/breaking-intel-exiting-the-server-business-selling-to-mitac/

 

[Nemesis11]

Actualmente, deve ser um divisão relativamente pequena. Por exemplo, os chassis eram da Chembro, as controladoras de storage penso que eram da Broadcom.

 

[Dark Kaeser]

Nada que não fosse esperado.

Intel Comments on New Layoffs, Budget Cuts in Client CPU and Data Center Groups​

We heard a rumor of an impending 10% budget cut last week but could not confirm the information. However, Dylan Patel of consulting firm SemiAnalysis tweeted that Intel planned to reduce its budget by 10%, resulting in "as much as" 20% layoffs in the impacted groups. We followed up with Intel, and the company issued the following statement to Tom's Hardware:

"Intel is working to accelerate its strategy while navigating a challenging macro-economic environment. We are focused on identifying cost reductions and efficiency gains through multiple initiatives, including some business and function-specific workforce reductions in areas across the company.

"We continue to invest in areas core to our business, including our U.S.-based manufacturing operations, to ensure we are well-positioned for long-term growth. These are difficult decisions, and we are committed to treating impacted employees with dignity and respect." Intel Spokesperson to Tom's Hardware.

https://www.tomshardware.com/news/i...get-cuts-in-client-cpu-and-data-center-groups

 

[Nemesis11]

Algo bastante interessante. Uma proposta da Intel de um ISA x86 64-bit "only" e "legacy free", com o nome "x86-S"

The long life of Intel® Architecture has resulted in a rich software ecosystem with an enormous installed base that extends from PCs to the cloud to mobile and from embedded devices to supercomputers and beyond.

Since its introduction over 20 years ago, the Intel® 64 architecture became the dominant operating mode. As an example of this evolution, Microsoft stopped shipping the 32-bit version of their Windows 11 operating system. Intel firmware no longer supports non UEFI64 operating systems natively. 64-bit operating systems are the de facto standard today. They retain the ability to run 32-bit applications but have stopped supporting 16-bit applications natively.

With this evolution, Intel believes there are opportunities for simplification in our hardware and software ecosystem.

Certain legacy modes have little utility in modern operating systems besides bootstrapping the CPU into the 64-bit mode. It is worth asking the question, “Could these seldom used elements of the architecture be removed to simplify a 64-bit mode-only architecture?”

What Would Be the Benefits of a 64-bit Mode-Only Architecture?​

A 64-bit mode-only architecture removes some older appendages of the architecture, reducing the overall complexity of the software and hardware architecture. By exploring a 64-bit mode-only architecture, other changes that are aligned with modern software deployment could be made. These changes include:

• Using the simplified segmentation model of 64-bit for segmentation support for 32-bit applications, matching what modern operating systems already use.
• Removing ring 1 and 2 (which are unused by modern software) and obsolete segmentation features like gates.
• Removing 16-bit addressing support.
• Eliminating support for ring 3 I/O port accesses.
• Eliminating string port I/O, which supported an obsolete CPU-driven I/O model.
• Limiting local interrupt controller (APIC) use to X2APIC and remove legacy 8259 support.
• Removing some unused operating system mode bits.

Software legacy correria em cima de virtualização:

Legacy Operating Systems on 64-Bit Mode-Only Architecture​

While running a legacy 64-bit operating system on top of a 64-bit mode-only architecture CPU is not an explicit goal of this effort, the Intel architecture software ecosystem has sufficiently matured with virtualization products so that a virtualization-based software solution could use virtualization hardware (VMX) to deliver a solution to emulate features required to boot legacy operating systems.

https://www.intel.com/content/www/u...visioning-future-simplified-architecture.html
https://cdrdv2.intel.com/v1/dl/getContent/776648

Se isto for para a frente, será bastante significativo a nível de hardware e software.

 

[Dark Kaeser]

Basicamente nada de novo durante a ISC23, a maior novidade a destacar é que, FINALMENTE, o Aurora está a funcionar, ainda não está completo.

A outra novidade, é que o Aurora tendo o o rácio de 2CPU + 6GPU por node, estarão disponíveis o 8UBB (2 CPU + 8 GPU por socket), se bem que estranhamente apenas nos sistemas Supermicro e Inspur

Speaking of OAM modules, Intel is using the show to announce a new 8-way Universal Baseboard (UBB) for Ponte Vecchio. Joining Intel’s existing 4-way UBB, the x8 UBB will allow for 8 Data Center Max GPU modules to be placed on a single server board, similar to what NVIDIA does with their HGX carrier boards. If Intel is to go toe-to-toe with NVIDIA and to capture part of the HPC GPU market, then this is one more area where they’re going to need to match NVIDIA’s hardware offerings. Thus far Supermicro and Inspur are signed up to distribute servers using the new x8 UBB, and if things go their way, these shouldn’t be Intel’s only customers.

Along with the UBB announcement, Intel is also providing for the first time a detailed, month-by-month roadmap for Data Center Max GPU product availability. Now that Intel has nearly satisfied their Aurora order, the first parts have been vaguely available to select customers, but now we get to see where things stand in a bit more detail. Per that roadmap, OEMs should be ready to begin shipping 4-way GPU systems in June, while 8-way systems will be a month behind that in July. Meanwhile OEM systems using the PCIe version of Ponte Vecchio, the Data Center GPU Max 1100, will be available in July. Finally, a detuned version of Ponte Vecchio for “different markets” (read: China) will be available in Q4 of this year. Details on this part are still slim, but it will have reduced I/O bandwidth to meet US export requirements.

a meia novidade o Falcon Shores (ainda versão SÓ GPU)

The cancellation of Rialto Bridge and the de-XPUing of Falcon Shores created a good deal of consternation within the media and HPC community, so Intel is using this moment to get their messaging in order, both in terms of why they pivoted on Falcon Shores, and just what it will entail.

The long and short of the story there is that Intel has decided that they mistimed the market for their first XPU, and that Falcon Shores as an XPU would have wound up being premature. In Intel’s collective mind, because these products offer a fixed ratio of CPU cores to GPU cores (vis a vie the number of tiles used), they are best suited for workloads that closely match those hardware allocations.

Now with that said, Intel is making it clear that they’re not aborting the idea of an XPU entirely; only that Falcon Shores in 2024/2025 is not the right time for it. So, Intel is also confirming that they will be developing a tile-based XPU as a future, post-Falcon Shores product (possibly as Falcon Shores’ successor?). There are no further details on that future XPU than this, but for now, Intel still wants to get to CPU/GPU integration once they deem the workloads and the market are ready. This also means that Intel is effectively ceding the mixed CPU-GPU accelerator market to AMD (and to a lesser extent, NVIDIA) for at least a few more years, so make of that what you will with Intel’s official rationale for delaying their own XPU.

Aurora Update: 10K+ Blades Delivered, Additional Specifications Disclosed​

Finally, Intel is also offering an update on Aurora, their Sapphire Rapids with HBM + Ponte Vecchio based supercomputer for Argonne National Laboratory. A product of two delayed processors, Aurora is itself a delayed system that Intel has been working to catch up on. In terms of the hardware itself, the light is in sight at the end of the tunnel, as Intel is wrapping up delivery of Aurora’s compute blades.

As of today, Intel has delivered over 10,000 blades for Aurora, very close to the final expected tally for the system of 10,624 nodes. Unfortunately, delivered and installed are not quite the same things here; so while Argonne has much of the hardware in hand, Aurora isn’t ready to make a run at the Top500 supercomputer list, leaving the AMD-based Frontier system to hold the top spot for another 6 months.

https://www.anandtech.com/show/1886...-shores-details-future-xpu-aurora-nearly-done

 

[Dark Kaeser]

Ainda em relação ao Aurora

Aurora Rising: A Massive Machine For HPC And AI​

Here is the kicker. When that last delay with the “Ponte Vecchio” Max Series GPU happened in October 2021, the plan was to have more than 9,000 nodes with a pair of “Sapphire Rapids” Xeon SPs – we didn’t know they would have HBM2e memory at the time – and six Ponte Vecchio CPUs rated at 45 teraflops at double precision floating point.

As it turns out, that peak theoretical number for a single Ponte Vecchio GPU was raised by 15.6 percent in 2022, to 52 teraflops at both FP32 and FP64. And knowing what we know today about the GPU counts, it would be easy to jump to a conclusion and multiply 52 teraflops – shown in the Max Series GPU chart in the Intel ISC presentation – by 63,744 GPUs in 10,624 nodes – the numbers shown in the specifications for the Aurora machine – and get 3.31 exaflops of aggregate peak theoretical compute for the Aurora 2023 machine. That would be a very big number indeed, and very exciting given that all Intel has said is Aurora would have “in excess of 2 exaflops of peak theoretical DP performance” thus far.

And as it turns out, that is not a correct conclusion to jump to. We had a hunch it wasn’t. Intel confirmed with us what the speed of the Ponte Vecchio GPU used in Aurora was.

What Argonne is actually getting is a Ponte Vecchio GPU rated at 31.5 teraflops, which is 61 percent of the peak performance of a standalone GPU, which means Aurora is only delivering just a hair over 2 exaflops of peak double precision floating point oomph. Intel has been clearly adding node counts to get above that 2 exaflops peak, and is not going to be adding one node more.

https://www.nextplatform.com/2023/05/23/aurora-rising-a-massive-machine-for-hpc-and-ai/

 

[Nemesis11]

What Argonne is actually getting is a Ponte Vecchio GPU rated at 31.5 teraflops, which is 61 percent of the peak performance of a standalone GPU,

Não sei onde isto está a ser medido, mas se o valor conseguido é apenas 60% do valor teórico, talvez esteja aqui a razão para o Rialto Bridge ter sido cancelado.
Não percebo bem é como é que a Intel se quer manter neste mercado, até 2025, só com este Ponte Vecchio e sem lançar nada.

 

[Dark Kaeser]

Pois, os primeiros slides sobre o Aurora listavam cerca de 9000 nodes, depois a Intel até anunciou que os números finais eram superiores (+16%), 9 que levaria a supor que a performance do Aurora seria superior aos 2 Exaflops, mas....

A explicação mais provável será manter os consumos.

 

[Nemesis11]

A explicação mais provável será manter os consumos.

É possível, mas aumentar o numero de nós de 9000 para 10624, vai levantar problemas na parte de rede.

Aurora should be at the top of the Top500 in November this year with a sustained performance of between 1.31 exaflops and 1.41 exaflops sustained on Linpack.

Vamos considerar alguns números:

• Frontier - Entrou no Top 500 em Junho 2022 - 1.1 Exaflops (1.2 Exaflops na lista de Junho 2023) - 22,7 MW
• Aurora - Novembro 2023 no Top 500? - 1.31 a 1.42 Exaflops? - 60 MW?

Olhando para o que era o Aurora inicial:

• 2018 (5 anos atrasado)
• Optane -> Cancelado
• Omni-Path -> Cancelado
• Xeon Phi -> Cancelado (O Substituto, Ponte Vecchio, na prática está cancelado)

Fora outros pequenos "detalhes". 300 milhões de $ ou mais que a Intel teve que colocar do próprio bolso. Só 75% dos 10624 nós têm a versão do Sapphire Rappids com HBM, porque não conseguiram entregar mais.

A Intel pode tentar acertar um numero ou outro, como na parte do consumo, mas para a Intel, este Supercomputador será sempre um desastre.

 

[Rafx]

O Aurora pode entrar na lista des supercomputadores, mas não deixa de ser um completo reflexo do que foi e continua a ser a Intel no últimos anos: uma empresa completamente à deriva a viver de louros passados.

As empresas são too big to fail.. até deixarem de o ser.

 

[Dark Kaeser]

Intel 14th Gen Core “Raptor Lake Refresh” allegedly launching October, “Sapphire Rapids Refresh” in early 2024​

• Raptor Lake Refresh-K: October 2023
• Raptor Lake Refresh non-K: November/December 2023
• Sapphire Rapids Refresh: early 2024 (Xeon W2500/W3500)
• Meteor Lake-H: Q4 2023
• Meteor Lake-S: Canceled
• Arrow Lake-S: Q4/2024 – Q1/2025

https://videocardz.com/newz/intel-1...october-sapphire-rapids-refresh-in-early-2024

 

[Dark Kaeser]

Argonne Aurora A21: All’s Well That Ends Better​

When it comes to a lot of high performance computing systems we have seen over the decades, we are fond of saying that the hardware is the easy part. This is not universally true, and it certainly has not been true for the “Aurora” supercomputer at Argonne National Laboratory, the second exascale-class system in the United States that has actually been installed.

Last Thursday, after heaven only knows how many days of work unpacking the blade servers comprised of a pair of “Sapphire Rapids” Max Series CPUs with HBM2e main memory and six “Ponte Vecchio” Max Series GPU compute engines, all 10,624 of the blades that are going into the 2 exaflops Aurora A21 system were finally and fully installed.

The Aurora saga that began even before Argonne announced the plan for the original 180 petaflops pre-exascale machine, which we have dubbed Aurora A18, in April 2015 based on Intel “Knights Hill” many-core processors and InfiniBand-ish Omni-Path 200 interconnects, scaling across a massive 50,000+ compute nodes. There were a lot of issues, particularly with Intel’s 10 nanometer processes used to make the compute engines but also with managing that level of concurrency across so many nodes and with trying to support emerging AI workloads on such a machine. And thus the original A18 machine architecture was killed off in March 2018 and the Knights Hill processor was killed off in July 2018. And instead of getting a pre-exascale machine in 2018, Argonne was promised a machine with in excess of 1 exaflops of sustained double precision floating point compute in 2021, which was dubbed Aurora A21, and it was not at all clear that it would be a hybrid CPU-GPU architecture given that Intel had not yet announced its intent to enter the datacenter GPU compute arena to take on Nvidia and AMD. That plan was revealed in March 2019, with Intel as prime contractor and Cray as the system builder.

The Aurora A21 machine, which is being installed here in 2023 after delays with the Ponte Vecchio GPUs and Sapphire Rapids CPUs, is a much better machine than Argonne was originally going to get and about as good as it could have expected for this year given the state of CPUs and GPUs here in 2023 as well. It has perhaps taken many more nodes to break that 2 exaflops peak performance barrier than either Intel or Argonne expected – we revealed last month that the Ponte Vecchio GPUs are geared down to 31.5 teraflops peak FP64 performance, significantly lower than the professed 52 teraflops peak performance of the device – but the resulting Aurora machine is a compute and bandwidth beast just the same. And it looks like Argonne got quite a deal on it, too – as was completely fair given all of the delays. Had it been possible to run the Ponte Vecchio GPUs at full speed, Aurora A21 would be rated at more than 3.3 exaflops peak, which would have made it the undisputed champion in the supercomputing arena for probably a few years.

As it stands, it looks like “El Capitan” at Lawrence Livermore will come in at in excess of 2 exaflops peak as well, based on AMD’s hybrid CPU-GPU devices, called the Instinct MI300A. How far in excess of 2 exaflops is unclear, but El Capitan only has to beat 2.007 exaflops to beat Aurora A21. With Lawrence Livermore in recent years playing second fiddle in the supercomputer performance to whatever machine that Oak Ridge National Laboratory has installed at roughly the same time, you an bet that Lawrence Livermore is angling to beat out Argonne on the November 2023 Top500 supercomputer rankings. We think it could be by 10 percent or more if the economics work out.

https://www.nextplatform.com/2023/06/27/argonne-aurora-a21-alls-well-that-ends-better/

 

[Dark Kaeser]

Intel Set to Exit NUC PC Business - Pushes Partners to Develop More SFF PCs

"We have decided to stop direct investment in the Next Unit of Compute (NUC) Business and pivot our strategy to enable our ecosystem partners to continue NUC innovation and growth," a statement by Intel reads. "This decision will not impact the remainder of Intel’s Client Computing Group (CCG) or Network and Edge Computing (NEX) businesses. Furthermore, we are working with our partners and customers to ensure a smooth transition and fulfillment of all our current commitments – including ongoing support for NUC products currently in market."

https://www.anandtech.com/show/1895...iness-pushes-partners-to-develop-more-sff-pcs

10 anos depois, é hora de dizer adeus ao NUC by Intel.

 

[Nemesis11]

Algo bastante interessante. Uma proposta da Intel de um ISA x86 64-bit "only" e "legacy free", com o nome "x86-S"

Software legacy correria em cima de virtualização:

https://www.intel.com/content/www/u...visioning-future-simplified-architecture.html
https://cdrdv2.intel.com/v1/dl/getContent/776648

Se isto for para a frente, será bastante significativo a nível de hardware e software.

Apesar de ser algo com uma distancia temporal grande, parece que este "x86-S" faz parte de um plano bastante radical para os próximos anos.
Há bastante tempo que existiam rumores que o Jim Keller tinha iniciado um projecto dentro da Intel chamado "Royal Core" e caso os primeiros rumores estejam correctos, é um projecto quase como uma folha em branco, relativamente aos cores anteriores.
O "x86-S" parece fazer parte desses planos e faz sentido que a Intel tenha divulgado este "x86-S" para daqui a uns anos o colocar em prática e não ser apenas algo "teórico".

Uma outra parte é ainda mais curiosa. Vão deixar de suportar Hyperthreading (SMT) para algo que actualmente se chama "Rentable Units".
Numa versão muito inicial deste "Royal Core", no "Lunar Lake", parece que o core suporta SMT, mas vai estar desligado e o que o "Diamond Rapids" terá 192 Cores com suporte "Rentable Units".

Algo que me chama a atenção são frases como "Extreme Focus on ST Performance" e "Extra Big Cores".

Isto é algo muito especulativo, mas a Intel, em 2016, comprou uma startup chamada "Soft Machines" que prometia o uso de vários Cores simultaneamente, numa thread. Artigo no Andndtech. É quase o oposto de SMT.
Além disso, a Intel e não só, tem vários papers sobre o assunto:

• Boosting Single-thread Performance in Multi-core Systems through Fine-Grain Multi-Threading
• Composable Lightweight Processors
• Overcoming Single-Thread Performance Hurdles in the Core Fusion Reconfigurable Multicore Architecture
• T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware

Pequenos excertos:

Core Fusion is a recently-proposed reconfigurable multicore architecture that attempts to circumvent this compromise by “fusing” groups of fundamentally independent cores into larger, more aggressive processors dynamically as needed. In this way, it accommodates highly parallel, partially parallel, multiprogrammed, and sequential codes with ease.

In this paper we propose Anaphase, a hardware/software co-designed threading scheme that leverages multiple cores to execute a single-threaded code. This scheme is based on a novel speculative multithreading technique that decomposes single-threaded applications in a fine-grain fashion. In this approach, the compiler is responsible for distributing instructions to cores whereas the hardware includes special components to support this execution model.

In this paper, we evaluate an alternative CMP design called Composable Lightweight Processors (or CLPs) to eliminate the problem of fixed-granularity processors. A CLP consists of multiple simple, narrow-issue processor cores that can be aggregated dynamically to form more powerful single-threaded processors. Thus, the number and size of the processors can be adjusted on the fly to provide the target that best suits the software needs at any given
time. The same software thread can run transparently without modifications to the binary on one core, two cores, up to as many as 32 cores in the design that we simulate.

Como disse, a Intel ter isto nos planos do "Royal" é uma enorme especulação minha e como os planos ainda estão a uma distancia grande, muito pode mudar ou nunca ter existido.
Por exemplo, outra hipótese completamente diferente é os cores usarem CMT (Volta Bulldozer está perdoado ).

Source dos rumores do "Royal Core":